Nope, that slide isn't talking about packed math. That slide is about higher IPC of NCU compared to CU - see a whole presentation and endnotes -> Exclusive: AMD VEGA Presentation
Nope, that slide isn't talking about packed math. That slide is about higher IPC of NCU compared to CU - see a whole presentation and endnotes -> Exclusive: AMD VEGA PresentationThe first slide here is talking about packed math instructions (and increased clock speeds), which is basically packing two FP16 instructions into an FP32 SP. Such an instruction can be an FMA instruction which is equal to two FLOPS, so in other words you then get a total of 4 FP16 FLOPS. NCU does indeed have double the FLOPS rate of GCN when it comes to FP16, but not for FP32 FLOPS
It either means higher performance per core per clock due to various improvements like scheduling and cache improvements, or it's referring to the FP16 packed math, resulting in double the IPC.Just a question to CatMerc and antihelten:
In that case, what they meant by this slide? Are they referring to SP ops/sec throughput with or without FMA?
End notes:
Isn't that what I just described?
What's the problem? A Memory catalog means absolutely nothing, especially for customers like AMD and nvidia.
Just look at samsung and nvidia, Samsung's memory catalog doesn't even contain HBM2 at all. How is it possible for nvidia to use HBM2 since last year?
that's what I'm trying to tell other ppl on other forums for months. Finally.Not only that. That type of HBM AMD used on fiji was never in their catalog too.
I agree to a point but I'm pretty sure all 1080tis can sustain 1900mhz or more consistently with a slightly noisy fan setting. Both my Titan XPs and my 1080TI were/are able to run consistently at 1950-1980 ('FE' all of them). I do really hope Vega kicks all their a$$es though.
You're assuming Vega is Polaris. It isn't.Also to your point, I wouldn't call 1900mhz 'overclocked' either. 2Ghz sure, but 1900mhz is pretty standard boost clocks right out of the box and the card doesn't need any tweaking to get there.
Separate but related question, I know the Linux driver log states maximum clock speed of 1600mhz but is that realistic of what the card would actually ship with? Seems like only the very best 580s just barely get to 1500mhz so I would think with a die that is nearly 3x larger and with 3x more transistors, they'd have trouble matching and OC'd Polaris 10, yet alone beating it. Nvidia had to drop clocks a bit on GP102 vs GP104 so I am thinking something similar may need to happen for Polaris 10 and Vega. Maybe GloFo has another revision of their 14nm process for Vega?
Looking forward to the announcements and specs. Seems like AMD has been out of the picture for far too long.
The easiest way to achieve higher performance from the same amount of cores, is to feed them properly, or increase amount of resources, like for example through increased Registry File Size.It either means higher performance per core per clock due to various improvements like scheduling and cache improvements, or it's referring to the FP16 packed math, resulting in double the IPC.
And clock speedThe easiest way to achieve higher performance from the same amount of cores, is to feed them properly, or increase amount of resources, like for example through increased(doubled) Registry File Size.
You're assuming Vega is Polaris. It isn't.
It was architected for higher clocks, think Kepler vs Maxwell.
It is not the same architecture, to the degree that it requires abstraction level to be backwards compatible with previous versions of GCN.Hmmm, good point. Well I know Vega and Polaris are different, but they are designed by the same company, on the same manufacturing process, and with what appears to be a pretty similar architecture as previous GCN cards. Though to your point, GCN 5.0 is new so maybe we could see something like Kepler to Maxwell.
Not to mention they have emphasized clock gating and Infinity Fabric with Vega that is highly reminiscent of the talk regarding Zen.It is not the same architecture, to the degree that it requires abstraction level to be backwards compatible with previous versions of GCN.
The applications have to be rewritten to take use of features that are apparent in Vega.
While the Steam Hardware Survey is hardly representative of forum users here, the vast majority even on this forum (although probably not the most active users) are using 1080p or 1440p monitors at 60Hz. 4K60 is gaining popularity, albeit slowly (the monitor upgrade cycle is 5-6 years if not more for most users), while high refresh rates at lower resolutions are only slightly ahead of this. And I'd say video cards that cost $400 and up are a niche market, not $800 and up, even if Nvidia probably sells 10x as many 1070s as 1080s (not to mention 1080Tis). And who here is talking about AMD having a "halo product" as fast as the 1080? I certainly don't expect that. Besides, CF and SLI scaling is bad enough that for it to make sense even in games that make use of it, your GPU budget needs to be significantly above the price of a 1080Ti - otherwise, a single card will perform better in the vast majority of cases. This wasn't the case just a few years ago.
This is also entirely disregarding all the idiots with more money than sense out there, that buy $1000 dual GPU card without actually knowing what they're buying - and then whining about it when there's no SLI/CF profile and their $1000 card performs worse than something half the price.
The gist of it: dual GPU cards only make sense as a barely-advertised .0001% niche product for people who specifically know what they're getting into. In any other case, it's a recipe for customer dissatisfaction and bad press.
Could you link me to that?
/**
* gmc_v9_0_mc_init - initialize the memory controller driver params
*
* @adev: amdgpu_device pointer
*
* Look up the amount of vram, vram width, and decide how to place
* vram and gart within the GPU's physical address space.
* Returns 0 for success.
*/
static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
{
u32 tmp;
int chansize, numchan;
/* hbm memory channel size */
chansize = 128;
tmp = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_CS_AON0_DramBaseAddress0));
tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
switch (tmp) {
case 0:
default:
numchan = 1;Thanks!https://cgit.freedesktop.org/~agd5f...drm/amd/amdgpu/gmc_v9_0.c?h=drm-next-4.13-wip
Code:/** * gmc_v9_0_mc_init - initialize the memory controller driver params * * @adev: amdgpu_device pointer * * Look up the amount of vram, vram width, and decide how to place * vram and gart within the GPU's physical address space. * Returns 0 for success. */ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) { u32 tmp; int chansize, numchan; /* hbm memory channel size */ chansize = 128; tmp = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_CS_AON0_DramBaseAddress0)); tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK; tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; switch (tmp) { case 0: default: numchan = 1;
AMD prepared for the meeting
AMD prepared for the meeting
I think Ryzen borders on miraculous. After being so noncompetitive for so long in the CPU space, Ryzen is an amazing design. Maybe they'll do the same with Vega Hopefully we'll see soon...... soon AMD? My $$$ are impatient to be spent.Makes you think... could a miracle really happen for AMD?
wtf is with the "Not log Skype"?
Weird, what does that have to do with AMD? It's not like they make phones, phone OS's or phone apps?Possibly related to Apple's IOS updates at end of last year where iPhones started recording skype calls on phone bills?
Isn't I/O channel width same for HBM1/2?Interesting that HBM mem channel size is 128bit. It should be 256 if memory serves (pun intended).
Not that that line says "or fail spectacularly" directly below it (partially obscured by the Ryzen logo). I take it it's a quote."Succeed Miraculously".
Makes you think... could a miracle really happen for AMD?