Because it costs a company time and money to do this. AMD could incentivize, or make easier, the transition to Zen (for x86) or Vega based cores with some software engineers.. and who better to help port code than AMD engineers.Why would AMD need to send engineers to port code? If you don't know how to code you wouldn't be in a position to need porting in the first place. It's not like any of the code is a new language.
Maybe not troll but have you never seen engineers being whimsical and prankish?I wondered about that as well when I read about the "infinity fabric". Seemed more about memory access and sharing then load balancing between GPUs, which is the main problem with multi GPU solutions.
Pretty surprised in this thread to see the fascination with similarity of naming schemes as well. Personally AMD can call the thing "FX5800 Ultra" and I wouldn't care, just want to see the parts.
I don't buy the "drivers not ready" theory, they've been working on this arch for years, big companies are not as inept as "Oops! We forgot to write the drivers!". AMD knows NV is selling a lot of Pascal these days and parts would be in stores if there was not something like "not enough HBM2 memory to launch" or "we aren't getting yields of functional chips per wafer on this revision to sell profitably".
Last, companies don't "troll" or "prank" in regard to product releases or press conferences. These are educated, middle to old aged people that are paid hundreds of thousands to millions of dollars. They are not 14 year old dumba$$es who "troll". Everything they do is aimed at presenting a professional, profit driven impression of the firm to investors. PR dept gets some latitude to do crap like "poor Volta" to pander to the fanboys, but you will NEVER see a CEO with a doctoral degree "trolling the industry".
I feel that this is exactly what we are witnessing. The end of an age and beginning of another.
To digress a bit, we have a technological tour de force in V100 resulting in a 800mm^2 monster die on a custom process. Not something a small company can replicate, so design around it. Don't go head to head. That's AMD future.
I am, about Navi.I don't know. I think developing a multi chip solution that's transparent to the system and game developers is exactly where they're heading.
I'm just not sure Vega or even Navi will be capable of that however.
I am, about Navi.
The latest slides presented shows Navi on 7nm, apparently soon after that process becomes available. We can be fairly certain that even a medium sized die will be prohibitively expensive to fab, at least for consumer GPUs. They appear to be banking on using the multi-die approach to overcome cost barriers. That is at least a 1 yr process advantage on the competition, even ignoring the other benefits of a seamless multi-die approach.
Q: Many argue that vega is just a refined polaris gpu, how would you respond to this ?
A: My software team wishes this was true
Vega is both a new GPU architecture and also completely new SOC architecture. It's our first InfinityFabric GPU as well
The new geometry pipeline in Vega was designed for higher throughput per clock cycle, through a combination of better load balancing between the engines and new primitive shaders for faster culling. As a programmer you shouldn't need to do anything special to take advantage of these improvements, but you're most likely to see the effects when rendering geometrically complex scenes that can really push the capabilities of the hardware.
RX will be fully optimized gaming drivers, as well as a few other goodies that I can't tell you about just yet
Missing a point there. It isn't about GDDR5X requiring a certain sized chip it's that at Vega's current size if they added it, it would be that much larger than it already is and 500mm2 seems to be sweet spot for large chips these days. So AMD would need remove HBM2 and probably other functionality and performance to get it down to size while supporting GDDR5X.@Valantar I'm an amateur so just arriving in this forum.
Titan Xp die size is less than 500mm2 using GDDR5X, suppose there are other reasons.
Not want to complain/flame/etc, just to inform as industry passionate.
This has been a wish of mine for a long time, but yeah, I don't think we'll see anything like that until Navi at the earliest.I think developing a multi chip solution that's transparent to the system and game developers is exactly where they're heading.
I don't buy the "drivers not ready" theory, they've been working on this arch for years, big companies are not as inept as "Oops! We forgot to write the drivers!". AMD knows NV is selling a lot of Pascal these days and parts would be in stores if there was not something like "not enough HBM2 memory to launch" or "we aren't getting yields of functional chips per wafer on this revision to sell profitably".
This has been a wish of mine for a long time, but yeah, I don't think we'll see anything like that until Navi at the earliest.
The primary issue that I can see with that as a business model comes down to bifurcation of the product stack. Right now, we get multiple cuts of different dies that result in ~5-9 SKUs. This aspect of lithography isn't going to go away anytime soon, there will be always be binning of silicon. OK, so now move to a world where we have some sort of HBM/Infinity Fabric/bridge chip of some kind that allows AMD to snap multiple GPU dies together transparently into new configurations. Assuming they work out the engineering behind it and it all works perfectly, how far do you take this multi-chip process?
I would assume they would only do it at the highest level possible (like all the previous X2 ATI/AMD GPUs of olde). At the same time, they could just as easily (in this theoretical world) toss 8 weaker chips together to form a high-end multi-chip. Which process would allow for higher margin?
Wait, I just realized something. This is Cell.
I'm going to combine these 2 a bit. Ok Raja, you're on.
1)Vega is a new architecture will higher throughput per clock than Polaris, AKA Vega better damn well have superior Performance-Per-Flop (PPF) compared to Polaris.
2) Developers don't have to do any work to harness this superior throughput (not counting HBCC).
3) AMD software driver teams WILL need to do work to see this true. But let me add another Raja quote.
Ok, so let's revise that #3.
3.1) AMD software driver teams will have optimizied for the "higher throughput per clock cycle".
BTW, I am being very generous with only wanted Vega to beat Polaris PPF. Overall, Hawaii still tends to be the PPF winner. As I discussed here, Vega (assuming 1525MHz) with Polaris PPF is 97% of an aftermarket 1080 Ti at QHD. If by the grace of god they can match Hawaii PPF, they will beat the 1080 Ti straight up. If they only mean to barely beat pathetic Fiji PPF though then forget about it.
Calling you out Raja. Drivers ready and better than Polaris PPF. If you over deliver (beat Hawaii PPF) I will buy your product...(also because that performance means it will beat the Titan Xp)
While I like your theory, do note that Raja specifically mentions a higher geometry throughput. In other words no increase in shader throughput, texturing, and all the other non-geometry work done by the GPU (per clock, I assume that is). This should balance out the architecture compared to for example Fiji, though.I'm going to combine these 2 a bit. Ok Raja, you're on.
1)Vega is a new architecture will higher throughput per clock than Polaris, AKA Vega better damn well have superior Performance-Per-Flop (PPF) compared to Polaris.
2) Developers don't have to do any work to harness this superior throughput (not counting HBCC).
3) AMD software driver teams WILL need to do work to see this true. But let me add another Raja quote.
Ok, so let's revise that #3.
3.1) AMD software driver teams will have optimizied for the "higher throughput per clock cycle".
BTW, I am being very generous with only wanted Vega to beat Polaris PPF. Overall, Hawaii still tends to be the PPF winner. As I discussed here, Vega (assuming 1525MHz) with Polaris PPF is 97% of an aftermarket 1080 Ti at QHD. If by the grace of god they can match Hawaii PPF, they will beat the 1080 Ti straight up. If they only mean to barely beat pathetic Fiji PPF though then forget about it.
Calling you out Raja. Drivers ready and better than Polaris PPF. If you over deliver (beat Hawaii PPF) I will buy your product...(also because that performance means it will beat the Titan Xp)
I find it very hard (impossible) to believe a new shader core CU (NCU) will result in zero increase in shader throughput per clock.While I like your theory, do note that Raja specifically mentions a higher geometry throughput. In other words no increase in shader throughput, texturing, and all the other non-geometry work done by the GPU (per clock, I assume that is). This should balance out the architecture compared to for example Fiji, though.
I don't see a problem with Raja/RTG saying "compared to everything else in our GPUs, we have enough shader throughput. Let's work on balancing out the architecture by strengthening its weakest points, and other than that focus on packed math." That makes perfect sense even in a non-resource limited scenario, and definitely does for someone as small as RTG taking on a Herculean task like modern high end GPU IC design (and driver development).I find it very hard (impossible) to believe a new shader core CU (NCU) will result in zero increase in shader throughput per clock.
The GPUs appear to be different to the degree that currently we may not see huge benefits from this architecture, so be prapared for huge initial disappointment. But the GPus are designed to handle high resolution gaming, thanks to incredible culling techniques. It is dependent on the developers to use those culling features from the architecture tho. Exatly the same case is for the Packed Math.Tahiti to Tonga to Polaris comparisons shows that "IPC" has increased since Hawaii (which outside of A Sync compute should be the same as GCN1). It's the 44CU:64ROP:384 GB/s (390) ratio that just brute forces past Polaris with its less balanced 36:32:256 ratio. (Ok, bandwidth shouldn't be used in the ratio here since it is separate from clocks... so I'm being mathematically inaccurate but hopefully you get my point).
So IPC only applies where things are equal, and Hawaii wins PPF through a better balance. Obviously Fiji is a mess for other reasons. I hope Vega's improvements make up for a still less balanced ratio than Hawaii.
Valantar, good point.
And it's not really a theory, just me putting the heat on Raja. I still think Vega could go anywhere from slightly faster than 1080 to faster than TXp.
increase in performance can come from next generation scheduling(load balancing) and from new pixel engine, that is detached from Memory controller, but client of L2 cache, rather.I don't see a problem with Raja/RTG saying "compared to everything else in our GPUs, we have enough shader throughput. Let's work on balancing out the architecture by strengthening its weakest points, and other than that focus on packed math." That makes perfect sense even in a non-resource limited scenario, and definitely does for someone as small as RTG taking on a Herculean task like modern high end GPU IC design (and driver development).
I find it very hard (impossible) to believe a new shader core CU (NCU) will result in zero increase in shader throughput per clock.
I don't see a problem with Raja/RTG saying "compared to everything else in our GPUs, we have enough shader throughput. Let's work on balancing out the architecture by strengthening its weakest points, and other than that focus on packed math." That makes perfect sense even in a non-resource limited scenario, and definitely does for someone as small as RTG taking on a Herculean task like modern high end GPU IC design (and driver development).
...which is where balancing out the architecture to ensure better utilization across all components comes in, no? I.e. exactly what I was saying.Thoretical FLOPS mean nothing if you cannot deliver real world gaming performance. Thats the major problem with GCN which Vega should address.
Didn't Raja state explicitly in the AMA that there was no need for developer effort to make full use of Vega?The GPUs appear to be different to the degree that currently we may not see huge benefits from this architecture, so be prapared for huge initial disappointment. But the GPus are designed to handle high resolution gaming, thanks to incredible culling techniques. It is dependent on the developers to use those culling features from the architecture tho.
I can't tell if you're agreeing with me, disagreeing, or perhaps somewhere in the middleincrease in performance can come from next generation scheduling(load balancing) and from new pixel engine, that is detached from Memory controller, but client of L2 cache, rather.
Throughput of the cores is enough, for this generation. Volta will disrupt massively, but AMD is not on a wasted position. We can see situation that right now AMD will be the go-to solution for high-end, and later Nvidia can come with Volta which will again turn the tide.
In theory, Raja is actually correct, because the nature of GCN architecture should be on par, clock for clock on the same level as GP100/Volta architecture. But all of this is neutralized by imbalanced design of the GPUs, and previously weak scheduling, and weak software, not to mention lack of culling, inefficient handling of Registry Files, and detachment of Pixel Engine from L2 cache, and being a client of Memory Controller(a lot of optimization required, and not being able to fully optimize the data delivery to cores).very true. I think NCU is one of the major architectural improvements in Vega to increase shader efficiency and utilisation. GCN has very bad real world gaming performance / FLOPS because of serious utilization issues. Hawaii with 6 TFLOPS barely matches GTX 980 with 5.1 TFLOPS. Fury X with 8.6 TFLOPS loses to GTX 980 Ti with 6.8 TFLOPS. Rx 480 with 5.7 TFLOPS barely matches GTX 1060 with 4.6 TFLOPS. Vega will address this major weakness of GCN.
Thoretical FLOPS mean nothing if you cannot deliver real world gaming performance. Thats the major problem with GCN which Vega should address.
I can't tell if you're agreeing with me, disagreeing, or perhaps somewhere in the middle
Not agreeing, nor disagreeing with you . Just adding something .I can't tell if you're agreeing with me, disagreeing, or perhaps somewhere in the middle
I hope this post helps you understand my way of thinkingHa, I just mean I get the same impression when you respond to me too. Such as telling me to prepare for disappointment and that AMD will rule the high end in the same post.
Yes it has in DX11 however AMD have been designing GCN from the start to fill that utilization with compute, which is why we see very large increases with async compute and compute heavy workloads in DX12 and Vulkan. Mantle was created for this to take advantage of their architecture and is now the basis of Vulkan and DX12.GCN has very bad real world gaming performance / FLOPS because of serious utilization issues.