Interposers are not very expensive, so we can please drop that recurring statement. Passive interposers are very simple (copper conductors), made on old processes and I doubt there is a yield problem. A 2012 article.
http://electroiq.com/blog/2012/12/lifting-the-veil-on-silicon-interposer-pricing/
"Sesh Ramaswami, managing director at Applied Materials, showed a cost analysis which resulted in 300mm interposer wafer costs of $500-$650 / wafer. His cost analysis showed the major cost contributors are damascene processing (22%), front pad and backside bumping (20%), and TSV creation (14%).
Ramaswami noted that the dual damascene costs have been optimized for front-end processing, so there is little chance of cost reduction there; whereas cost of backside bump could be lowered by replacing polymer dielectric with oxide, and the cost of TSV formation can be addressed by increasing etch rate, ECD (plating) rate, and increasing PVD step coverage.
Since one can produce ~286 200mm2 die on a 300mm wafer, at $575 (his midpoint cost) per wafer, this results in a $2 200mm2 silicon interposer."
HBM stacks can be costly due to manufacturing difficulties. You have to assemble 5 die at a minimum to very small tolerances. Thousands of micro-bumps at 55 micrometer spacing. Errors at any one stage wastes all 5 die. This is what I believe is restraining quicker adoption.