“Not all 10nm technologies are the same,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel. “It’s now becoming clear that what other companies call a ‘10nm’ technology will not be as dense as Intel’s 10nm technology. We expect that what others call ‘7nm’ will be close to Intel’s 10nm technology for density.”
It wasn’t always like that. Traditionally, chipmakers scaled the key transistor specs by 0.7X at each node. This, in turn, roughly doubles the transistor density at each node.
Intel continues to follow this formula. At 16nm/14nm, though, others deviated from the equation from a density standpoint. For example, foundry vendors introduced finFETs at 16nm/14nm, but it incorporated a 20nm interconnect scheme.
Technically, the foundries didn’t introduce finFETs at a full node (14nm), but rather at a half node. TSMC, for one, calls it 16nm.
Still, foundries found a way to provide value to their customers at 16nm/14nm. “Foundries are less fixed on sticking to a 0.7X pitch shrink per node and more on providing their customers with some combination of power, performance, area and cost benefit at a half-node cadence,” said Mike Chudzik, senior director of strategic planning at Applied Materials