- Mar 12, 2006
- 2,708
- 0
- 0
A little Verilog question that has been driving me up the wall: why does the following code produce undefined values in the assign statement and correct values in the display statement?
assign cache_uid = (transmit_uid & {uidw{transmit}}) | (receive_write_uid & {uidw{receive}}) | (outstanding_write_uid & {uidw{outstanding}}); $display("cache_uid=%h, try again=%h", cache_uid, (transmit_uid & {uidw{transmit}}) | (receive_write_uid & {uidw{receive}}) | (outstanding_write_uid & {uidw{outstanding}}));
And printed in the console display:
cache_uid=XX, try again=88
assign cache_uid = (transmit_uid & {uidw{transmit}}) | (receive_write_uid & {uidw{receive}}) | (outstanding_write_uid & {uidw{outstanding}}); $display("cache_uid=%h, try again=%h", cache_uid, (transmit_uid & {uidw{transmit}}) | (receive_write_uid & {uidw{receive}}) | (outstanding_write_uid & {uidw{outstanding}}));
And printed in the console display:
cache_uid=XX, try again=88