Of course it sucks -- depending upon the version of the C3, it's FP unit, although (partialy) pipelined, is clocked at 1/2 the frequency of the rest of the core. That and it decodes exactly 1 x86 instruction per cycle, as compared to up to 3 on the Athlon family (and although the P4 only is able to decode 1 x86 instruction per cycle, it can issue more uops from the trace cache than a "typical" x86 instruction is broken up into). Add to that its lower frequency, and that its FSB is still limited to 133mhz (recall that the P3's with a 133mhz FSB didn't gain much from DDR, other than the reduction in memory latency).
PS -- Assimilator -- beware when you disparage Cyrix's; The Kooshie hears all