VIA's memory controller vs. Intel's

[CBone]

Comparing the memory systems for VIAs p4x266 against the same for intels 845, what are the real world meaning of the changes?

On the VIA side, VIA has bumped up the IOQ depth to 8, and "the new memory controller with Performance Driven Design can burst up to eight Quad Words of data per clock, up from four in previous designs."

On Intels side, the 845 has increased the IOQ depth to 12 and upped the open pages to 24.

What does this mean in terms of performance enhancing? Could someone explain this other than "the old number was x, this is x +3, it is increased," that web p/reviews slip out if they even mention it?

Does a beefed up ddr controller beat a REALLY beefed up sdr controller running at overclocked peak?

Cbone

 

[EricHagen]

<< Does a beefed up ddr controller beat a REALLY beefed up sdr controller running at overclocked peak? >>



lol That's an interesting way to put it.

can you please differentiate between "beefed up" and "REALLY beefed up".


But I guess, the DDR would be faster, simply because it has a higher throughput. The technology behind reading the data off a DDR bus is not really that different from that of a SDR bus except that the data is coming in twice as fast as the instructions are going out.

The comparison is just nitpicking. So you want to try to compare an overclocked SDR system against a DDR system? Well, if you can get a 100% overclock out of the SDR system, sure it will be faster than a similarly clocked DDR system.

So?

The point I'm making is that you can't compare like that.

If you want to say "what does the increase in the IOQ actually accomplish" then the question gains a bit of validity.

But, with IOQ and things, they're just queues that buffer data so that the memory bus doesn't have to wait for the chipset to clear its data before it can begin a new access. There is a point of diminshing returns. I assure you that Intel and AMD have researched thisa and the numbers they're using represent a nearly optimum value to most effectively use the FSB and MEM bandwith of their particular system.

I would guess that further doubling the IOQ depth would do nothing but increase the transistor count, heat output and perhas cycle time (decreasing clockspeed).

So in that sense, there is NO such thing as a "REALLY beefed up" design as you might be thinking of it.

If it were as simple as adding another 12 quads to the IOQ, don't you think they would have thought of that already? =-)

Eric

 

[CBone]

<< If it were as simple as adding another 12 quads to the IOQ, don't you think they would have thought of that already >>



Yes, but in all of the BIOS guides and manuals, upping the IOQ comes with the warning that stability may be compromised. Has this been overcome or have compromises been made? Which changes will actually result in higher performance and which are just bigger numbers made for the sake of having bigger numbers? "Hey, I can get this stable at x + 4 now." "Does it help any?" "Not really, but I can do it, and it's bigger. Marketing will like having more ammo."

"Beefed up" vs. "REALLY beefed up" is the same as a small change vs. a rather large change. I guess that could have been more clear. The real world difference between ddr and sdr isn't really that large. Let's say if you bump up ddr performance by 4% and sdr by 20%, how close are they now? If ddr starts out with higher latency than sdr, and the sdr is being pushed in a way that increases it's latency slightly or doesn't change it, but is using an advanced controller to wring more apparent speed out of it, who wins? Say you have the somewhat advanced ddr running at say 300MHz head-to-head against the more advanced sdr running at 175MHz.

I'm still foggy on the open pages thing, though.

About the nitpicking, when things are apparently very close, making a decision comes down to informed nitpicking.

Cbone

Is that Ames, IA? I'm an Iowan, I had a lot of friends in Ames way back when.

 

[Sohcan]

<< I'm still foggy on the open pages thing, though. >>

DRAM is organized into banks, which are logically arranged as a number of 1-bit DRAM cells in a 2D array and selectable by a column and row address. SDRAM usually has 4 banks per chip, and with 4-16 chips per DIMM, a DIMM has 16-64 banks.

If you want to access main memory, there is a certain amount of latency between the FSB and the chipset, then the chipset to the DRAM (2-3 FSB cycles). The address selects a certain bank, and the proper row is selected and the bank's sense amps have to be charged (2-3 cycles, which is the RAS latency (row access select)). Then the proper column is selected, and after 2-3 more cycles (CAS latency), the DRAM begins bursting the first word.

But SDRAM and RDRAM are multibank architectures; they can keep a certain number of banks "open." In a particular bank, the last accessed row can be kept open, and the memory controller can keep a limited number of banks open at a time. If you try to access a row that is already open, you do not need to do the RAS latency, so you can immediately access the column, which can cut 2-3 cycles from the access time (this is a page hit). If you try to access a row within a bank that has no rows open, you have to do the RAS and CAS latencies (this is a normal page miss). On the other hand, if you try to access a row in a bank that has another row open, the sense amps have to write back the old row, which adds 2-3 cycles (the precharge latency); in this case, you have to do the precharge latency, then the RAS and CAS latencies.

But since most memory accesses are somewhat serial, most of the time you'll get a page hit. The actual page hit rate depends on the number of banks you can keep open at a time. There was an article from Ace's hardware from about a year ago that said the typical page hit rate is about 55%, the normal page miss rate is 40%, and the precharge rate is about 5%.

 

[CBone]

Thanks for the breakdown, Sohcan.

Cbone