VIA's "Secret Weapon" - Muahahaha!

[MadRat]

Every VIA chipset since the Apollo Pro 133a has supported memory interleaving. Why would their DDR chipset be any different? If you beleive that the P4+DDR chipset will be drastically worse then you are mistaken. There is absolutely no reason an interleaved-DDR board would not perform equal to a RAMBUS-based moard. People way overestimate the advantage of RAMBUS's bandwidth for most jobs.

 

[WindBoy2000]

goo goo gaa gaa, what he just say?

 

[ST4RCUTTER]

Madrat,

Interleaving wouldn't help, the P4's 8K L1 cache was designed to take advantage of the 16bit wide path to the memory bus at high frequency (400MHz) used by RDRAM. If you force that tiny L1 cache to try and use a 64-bit wide data path with half the refresh cycles it will choke, and the penalty will be a serious latency penalty.

 

[Midnight Rambler]

<< Obviously this precedent you speak of isn't guaranteed to apply, or else via wouldn't risk money on it. via hasn't violated ANYTHING until the courts say so! >>

The point is, the courts already said so, in the previous case I referred to. Unless VIA could prove that this situation is out of the scope of the first legal ruling against them, there would be no doubt they would lose (if Intel would contest) as court rulings are most often based on prior precedent/case law. And IIRC, the precedent-setting case was ruled on at the state Supreme Court level. That's a pretty big trump card ...

Yeah 'Wingz, I'm sure the AMDer's are hatin' that you now own the EV bus ... will that be accretive to Intel earnings in the first year?

 

[MadRat]

If a case is settled then the court did NOT decide. All aspects of the case become void if Intel settled. I don't remember the legal name for this, but basically Intel gave up the claim to judgement by settling. Once you give up the claim it requires an entirely new lawsuit to re-establish your case. VIA could use the settlement for grounds of a countersuit, being that Intel has set precedence to let competitors pay royalties after the fact without adding punitive damages. Its all very complicated. Matters if Intel really settled outside of the court, or if the jugde accepted an arbitrary deal between the parties.

 

[formulav8]

If you ask me I think Intel deserves it.




Jason

 

[Wingznut]

Ok, I'll ask you. Why do you think Intel deserves it?

 

[grant2]

Interleaving wouldn't help, the P4's 8K L1 cache was designed to take advantage of the 16bit wide path to the memory bus at high frequency (400MHz) used by RDRAM. If you force that tiny L1 cache to try and use a 64-bit wide data path with half the refresh cycles it will choke, and the penalty will be a serious latency penalty.

interleaved DDR ... 100mhz x 2 x 2 ... seems like 400mhz to me?

besides, can't the chipset massage the data to get it into four 16bit chunks to appease the cpu? (sort of mommy cutting her little boy's steak for him haha, good analogy for the p4)

 

[MadRat]

I don't see why breaking the 64-bit data into 16-bit chunks would be difficult. If that is the case then I seriously doubt that there is no penalty for recompiling the 16-bit data back into 64-bit chunks.

Intel most likely has some sort of bypass for non-RAMBUS data. If you look at the SDRAM version of the P4 then you'll see that Intel actually made the packaging different for each version; mostly different is the re-location of outer pins to the interior of the CPU.

What if RAMBUS actually slows down the I/O of the CPU? Ever thought of that? Huh? Huh? *pokes ST4RCUTTER in the belly to be rather annoying, at least until he replies*

 

[odog]

<< That's why the NatSemi logo appears on newer Via chips. >>

VIA bought natsemi, thats why they have that logo. VIA also subbed out all of their production to natsemi before they bought them, at that point they didn't have the N logo on the chips.

VIA getting the S3 patents was more of a coup then anyone realizes.. S3 held some sort of important patent that the Itanium is very dependent on. without that patent intel would have had to redesign the itanium heavily. they decided to just pay S3 for the right to use the patent, which S3 was more then happy to do.(since this was right after the virge bust and they needed cash badly)

basically it means, VIA has intel by the balls on P4 chipsets, and most likely has the right to realease a itanium chipset as well.

 

[ST4RCUTTER]

What if RAMBUS actually slows down the I/O of the CPU? Ever thought of that? Huh? Huh?

Trying to be flip eh...

I don't see why they couldn't engineer a board to do what you're saying, but it's not as easy as just chopping the data off the 64bit path into 16-bit pieces. You have to take that data and double pump it again to achieve 4X to keep pace with the P4 scheme and also ensure that everything stays syncronous. Good engineers are everywhere though, so this is certainly achievable for a price.

 

[Degenerate]

<< is there a technical reason DDR cannot be dual-channeled to the p4 like rdram is? >>


It can but the CPU is designed to take Rdram. A change to DDR would mean a little bit of redesign.

 

[grant2]

is there a technical reason DDR cannot be dual-channeled to the p4 like rdram is?
It can but the CPU is designed to take Rdram. A change to DDR would mean a little bit of redesign.

I think you are mistaken and it's the chipset that must be redesigned (replaced) to use a different ram type.

Although it's arguable that sdram will improve or decrease p4 performance (we'll find out soon enough!) the cpu shouldn't need any changes to work.

 

[MadRat]

1. The key to knowing if DDR has a chance is that the core of the chip uses 64-bit pathways.

2. It doesn't make sense to recompile then decompile the 64-bit information for every I/O.

3. I just have this suspicion that Intel has a bypass for native 64-bit input. Intel knew of both memory technologies well before the release of the P4 design. I'm guessing they had plenty of forethought to use DDR efficiently.

4. Is VIA even ready for Socket-478? All this talk about P4 chipsets will be mute if they are not ready for Socket-478. Intel is likely to drop the current P4 socket just to stifle their innovations a little longer.

 

[grant2]

3. I just have this suspicion that Intel has a bypass for native 64-bit input. Intel knew of both memory technologies well before the release of the P4 design. I'm guessing they had plenty of forethought to use DDR efficiently.

if they had that much forethought why did they sign this rambus-only contract they're apparently trying to wriggle out of?

IMHO someone intel thought that p4 + rdram was a slam dunk, back before AMD &amp; tech slowdown put the screws to their profit margins.