You are taking his quote completely out of context. It has nothing to do with multi-die interposer design like you are talking about.
If you want to discuss crazy theories of how graphics cards will ditch proven and well-understood designs for some insane asymmetrical multi-die mid-range interposer design, go start a new thread in the AMD/NV sub-forum. There is no need to take Pascal/Polaris GPU threads out of context with these wild theories. This is the same garbage we read on Fury X being a dual-chip design and now this non-sense is being regurgitated again for Pascal and Polaris.
Fact is, you provided no proof/logical reasoning at all why AMD/NV should suddenly abandon the large monolithic die strategy considering it has worked so well for them for the last 20+ years. Even AMD has now adopted this strategy full force with 290X and now Fiji.
Everything you described is the complete opposite of simplifying GPU design. Making multi-die graphics card where one die has certain parts and the other has other parts and making them work together as 1 cohesive unit, while overcoming latencies, using complex interposer, having Windows/driver see multiple die as 1 GPU vs. just fabbing a larger die single chip as 14nm/16nm node matures is the definition of complexity.
Again, there is no logic to your idea whatsoever. Even if your idea could work, the industry is moving towards larger SoCs, integrated designs, 3D memory, reduction of latencies and larger die. So really, it's actually YOU with the wild theories that has to convince the rest of the world that it makes sense and thus far it's not convincing at all.
It's even crazier to think that it would be better to take a 600mm2 die and split it into 2 smaller die, asymmetrical units in each of those die because now you are increasing the part's chance of failure. If die 1 has a 5% chance of failure and die 2 has a 5% chance of failure, the chance of failure for the single PCB graphics card would be 1-0.95*0.95 = 9.75%. Your idea not only increases complexity, but it increases RMA costs.
You also didn't address how the hell is it better to take 2 mid-range GDDR5(X) chips and combine them on an interposer vs. a single 500-600mm2 HBM2 design.
A year? Not a chance. Even if AMD/NV could build 2 die on an interposer, they won't be able to solve the OS/driver seeing them as 2 separate chips for SLI/CF. Besides, there are far better ways to increase performance over time such as feeding massive amounts of memory bandwidth to the GPU by stacking the memory directly onto the GPU and pushing the limits of die area as 7nm, 10nm, 14nm/16nm nodes reach maturity.
Yes, because 1000s of engineers at AMD/NV think there is a better way. When over the next 5 years we see 2nd and 3rd generation 14nm/16nm FinFET maturity and die sizes start approaching 780Ti/980Ti/Fury X levels, what's going to be your response? There is sufficient technology in place to continue using proven techniques.
After reading this, I feel compelled to reply. Please forgive the lengthy post.
You are taking his quote completely out of context. It has nothing to do with multi-die interposer design like you are talking about.
My point was that AMD can mix and match IP blocks much easier than you seem to believe, allowing them to produce non-traditional parts quickly, and at cost effective points. I never said he meant multi-die interposer in the statement.
If you want to discuss crazy theories of how graphics cards will ditch proven and well-understood designs for some insane asymmetrical multi-die mid-range interposer design, go start a new thread in the AMD/NV sub-forum. There is no need to take Pascal/Polaris GPU threads out of context with these wild theories. This is the same garbage we read on Fury X being a dual-chip design and now this non-sense is being regurgitated again for Pascal and Polaris.
Are you the thought police or a mod?
It seems that once you see the words multi-die you think with blinkers. The previous concepts all assumed a Xfire arrangement. Even with what is now known about interposers, and their ability to connect discrete die, you are still stuck in this line of thinking and lumping all multi-die as a single concept, even assuming that multi-die MUST mean identical subcomponents with duplicated wasted blocks.
Fact is, you provided no proof/logical reasoning at all why AMD/NV should suddenly abandon the large monolithic die strategy considering it has worked so well for them for the last 20+ years. Even AMD has now adopted this strategy full force with 290X and now Fiji.
I have never claimed to have proof. In fact, I have always claimed that this is speculation. Reasoned speculation, but speculation nevertheless. logical reasoning however is another matter. Read on.
As to why AMD would abandon the large monolithic die strategy, you just have to read what AMD themselves wrote on many occasions. These are just two samples from 2013.
Remember that UofT paper you ridiculed? Titled" Enabling Interposer-based Disintegration of Multi-core Processors". Maybe you should actually read it before you criticize. One of the three authors is an AMD employee. There are other papers, some into semi-active/active interposers, also with AMD employees as co-authors.
Die Stacking is Happening. A pdf by Bryan Black of AMD. Headline quotes from some slides.
SI Integration Is Running Out Of Gas.
Die stacking is ideal for integration.
Die Stacking Motivation (large die yield is getting worse).
Interposer Will Be The SOC With Multiple 3D Components.
Everything you described is the complete opposite of simplifying GPU design. Making multi-die graphics card where one die has certain parts and the other has other parts and making them work together as 1 cohesive unit, while overcoming latencies, using complex interposer, having Windows/driver see multiple die as 1 GPU vs. just fabbing a larger die single chip as 14nm/16nm node matures is the definition of complexity.
This paragraph has so many misconceptions.
The U of T paper says, "the impedance across the interposer is identical to conventional on chip interconnects". Do you know what this means for latency?
Complex interposer? What a joke. It's a network of wires in this case, no active components.
There is NO multiple die to the Windows/driver. In fact there is ONE interposer based GPU.
Read the research papers to see why fabbing a larger single die if you can fab smaller components is the essense of mediocrity.
Again, there is no logic to your idea whatsoever. Even if your idea could work, the industry is moving towards larger SoCs, integrated designs, 3D memory, reduction of latencies and larger die. So really, it's actually YOU with the wild theories that has to convince the rest of the world that it makes sense and thus far it's not convincing at all.
"Die Stacking is Happening" pdf. The industry is needing/trying to move away from traditional single masked integration.
It's even crazier to think that it would be better to take a 600mm2 die and split it into 2 smaller die, asymmetrical units in each of those die because now you are increasing the part's chance of failure. If die 1 has a 5% chance of failure and die 2 has a 5% chance of failure, the chance of failure for the single PCB graphics card would be 1-0.95*0.95 = 9.75%. Your idea not only increases complexity, but it increases RMA costs.
Assuming a 5% failure rate to prove a point is so amateurish and arbitrary.
Do you think the failure rate for 18 billion transistors is the same as 9 billion? Right there the first assumption is wrong. Individually the failure rates between the die sizes are different.
Once the composite/combined failure rate is below a certain acceptable level, the product is marketable. You should know this.
You also didn't address how the hell is it better to take 2 mid-range GDDR5(X) chips and combine them on an interposer vs. a single 500-600mm2 HBM2 design.
This is a good one. Do you realize you're contradicting yourself? In an earlier post you made the argument for both AMD and Nvidia releasing a mid range die (300mm^2) this year and gradually raising the size to the 600mm^2 level over a couple years. How can you now claim that a mid-range die is GDDR5(X), unless you are saying that the top chips to be fabbed this year, using your argument, will abandon HBM. One of these statements must be false. if they are using HBM, which is what all indications are trending, then the interposer is used and your argument is voided.
As to being better, an engineering cost analysis has determined it's cheaper [once an interposer is already in use] and can also lead to better binned units. Read the research.
Yes, because 1000s of engineers at AMD/NV think there is a better way. When over the next 5 years we see 2nd and 3rd generation 14nm/16nm FinFET maturity and die sizes start approaching 780Ti/980Ti/Fury X levels, what's going to be your response? There is sufficient technology in place to continue using proven techniques.
Read the published papers starting several years ago by AMD themselves. They WANT to dis-integrated complex monolithic die and use 2.5D interposer based tech to reintegrate the sub-units. They identified, several years ago, the necessary research to accomplish this. They have, in my opinion, done the necessary steps for commercial products to be released.
Potential future if this happens:
Composite GPUs, possible asymmetry in design of sub units.
Cheaper to fab GPUs might translate to lower prices eventually with competition.
For AMD now, assuming Nvidia lagging, is a higher performing product than the competition.
The 600mm^2 tradition max GPU is no longer the limit. Interposers are not reticle limited.
Each sub-unit can use the best process for the type of circuits contained within.
More golden sample die bins can be produced.