AMD Polaris 10 and Polaris 11 to succeed Radeon Fury and Radeon 300 series
According to the new roadmap, that is slightly more informative than a graph shown at Capsaicin, Polaris architecture might replace both Radeon Fury and Radeon 300 series. This roadmap clearly suggest that all chips might be replaced with silicons based on Polaris architecture. Does this mean there are are no rebrands in Radeon 400 series? Well it might be hard to answer this question right now, but that would be a very good move from AMD.
AMD Radeon R9 490 and R9 480 based on Polaris 10?
New roadmap also sheds some light on what to expect from Radeon 400 series GPU positioning. I think it is highly unlikely Fury series will disappear, instead both Fury and Polaris 10 cards should coexist on the market for some time. AMD otherwise wouldnt release Radeon Pro Duo, if they were not planning to continue Fiji production.
Also you might have noticed that Fury Series block is much smaller than Polaris 10 block. It could further suggest that Polaris 10 will be used on more cards than just R9 490 series. Polaris 10 could therefore launch as R9 490 and R9 480 series, which I think makes a lot of sense now.
Meanwhile Polaris 11 would fill everything in mid-range and entry-level segments. If Im right, then AMD made one of the best decisions in years. Rather than keep rebranding existing cards, they are focusing entirely on new architecture. This way if you ever hear about Radeon 400 series, you will immediately know its power efficient 14nm FinFET GCN 4.0 architecture.
Furthermore this roadmap also confirms that Polaris 10 and 11 will support HEVC de/encoding and HDMI 2.0, DisplayPort 1.3
AMD Vega and Navi
Moreover, we are told that AMD Vega, first architecture with HBM2, will arrive next year (2017). I think this is important, because some of our readers that were literally counting pixels on Capsaicin graph, were still hoping for late 2016 launch. Well this roadmap clearly says there is no Vega this year, but well its just a roadmap, it can always change.
In 2018 AMD will unveil its new Navi architecture that will bring NextGen memory. For now AMD representatives refuse to describe what is hidden behind this phrase.
Also I encourage you to check our new page dedicated to GPU Roadmaps, where we keep the latest information about hew chips.
HBM2 seems plenty nextgen to me. What could Navi's "NextGen" possibly offer that HBM2 won't??
I predict Navi will be multi-die on an interposer. Linked up, they will behave as one large chip.
So AMD is following Nvidia's strategy now of small die first and hoping it leads to bigger profits.
This has the logic as a small part of the total area so a memory process would be more efficient. GPU logic is the reverse of CPU with regards to size ratios. Not sure it would work in that case.my guess is that they will fuse the gpu and memory circutry in the same die.
like this: http://www.eetimes.com/document.asp?doc_id=1261018
I'd say that's pretty much confirmed, hint scalability :sneaky:I predict Navi will be multi-die on an interposer. Linked up, they will behave as one large chip.
HBM2 seems plenty nextgen to me. What could Navi's "NextGen" possibly offer that HBM2 won't??
Agree with PIM. Cuts down on data transfers so saving power and increasing performance.I believe it will be PIM (processing in memory).
Also,big pro series GPU could be multidie on interposer,cosumer space not so sure.
It all depend on your goal. If you target the best Perf/Watt, then its not competitive. For best yields on production, yes multi die is a good solution.Navi is clearly multiple dies on an interposer, there's only one way ahead for silicon.
I predict Navi will be multi-die on an interposer. Linked up, they will behave as one large chip.
AMD is working on a coherent data fabric that will eliminate PCIe latency, the first product to receive this technology will be an upcoming exascale-class HSA (Heterogeneous System Architecture) multi-chip-module (MCM) for the server market.
The new interconnect method will offer nearly seven times more performance than the traditional PCIe interface: four Global Memory Interconnects (GMI) will reportedly offer a latency-free 100GB/s link between the CPU and GPU, much more than the 15GB/s at about 500ns latency provided by PCIe x16.
The first MCM with the coherent fabric will reportedly feature a Zeppelin CPU (presumably with Zen-based cores) and a Greenland GPU with High Bandwidth Memory (HBM) on the same chip package. The slide below reveals the Greenland GPU promises 4 teraflops of raw computing power and mentions there's a 500GB/s link between the GPU and the HBM.
The chip will support DDR4-3200 memory, which will talk to the CPU at the same 100GB/s. The product is expected sometime in the 2016-2017 timeframe.
Agreed, but why do you think its absolutely necessary to move a lot of data between processing units.It all depend on your goal. If you target the best Perf/Watt, then its not competitive. For best yields on production yield, its a good solution.
PS: what cost the most energy in today's GPUs is not calculation, but moving data. And moving data between GPUs will kill the efficiency compared to a single die...
It all depend on your goal. If you target the best Perf/Watt, then its not competitive. For best yields on production yield, its a good solution.
PS: what cost the most energy in today's GPUs is not calculation, but moving data. And moving data between GPUs will kill the efficiency compared to a single die...
NEC designed eDRAM die includes additional logic (192 parallel pixel processors) for color, alpha compositing, alpha blending, Z/stencil buffering, and anti-aliasing called “Intelligent Memory”, giving developers 4-sample anti-aliasing at very little performance cost.
20 years for a patent in the US. Very interesting stuff nonetheless
starting with a system with a separate CPU chip and DRAM chip(s), add small amounts of "coprocessor" computational ability to the DRAM, working within the limits of the DRAM process and adding only small amounts of area to the DRAM, to do things that would otherwise be slowed down by the narrow bottleneck between CPU and DRAM: zero-fill selected areas of memory, copy large blocks of data from one location to another, find where (if anywhere) a given byte occurs in some block of data, etc. The resulting system—the unchanged CPU chip, and "smart DRAM" chip(s) -- is at least as fast as the original system, and potentially slightly lower in cost. The cost of the small amount of extra area is expected to be more than paid back in savings in expensive test time, since there is now enough computational capability on a "smart DRAM" for a wafer full of DRAM to do most testing internally in parallel, rather than the traditional approach of fully testing one DRAM chip at a time with an expensive external automatic test equipment.[1]
So AMD is following Nvidia's strategy now of small die first and hoping it leads to bigger profits.
Yes the US has massive problems. We just act oblivious and better than everyone20 years for a patent in the US. Very interesting stuff nonetheless