VISC CPU 3X the IPC?

[witeken]

The most useful part of that slide, IMO, is the comparison of the Apple Cyclone, ARM A15, ARM A57, and Haswell.

How accurate is it, though? IIRC, Saltwell's pipeline (16 stages) is at least as long as Haswell. And what are the clock speeds?

Edit: nvm the pipeline comment because they used Silvermont not Saltwell, but I think Cyclone's is longer.

 

[Nothingness]

How accurate is it, though? IIRC, Saltwell's pipeline (16 stages) is at least as long as Haswell. And what are the clock speeds?

Edit: nvm the pipeline comment because they used Silvermont not Saltwell, but I think Cyclone's is longer.

Interesting comment about pipeline length... Haswell branch misprediction penalty is 15-20 cycles, while Cyclone is 14-19 cycles. To me this means two things: both CPUs are as deep (so the slide is not accurate), and Cyclone pipe stages are rather short which probably means frequency can be increased well beyond the current level (though probably with a too high power requirement).

 

[Arachnotronic]

Interesting comment about pipeline length... Haswell branch misprediction penalty is 15-20 cycles, while Cyclone is 14-19 cycles. To me this means two things: both CPUs are as deep (so the slide is not accurate), and Cyclone pipe stages are rather short which probably means frequency can be increased well beyond the current level (though probably with a too high power requirement).

Sounds like extra gas in the tank for future chips, particularly built on 14/16 FinFET.

 

[Atreidin]

I'm skeptical. However I don't doubt that we'll see super-fans touting how awesome it is, even after real-world products don't show the predicted theoretical performance.

 

[Enigmoid]

Interesting comment about pipeline length... Haswell branch misprediction penalty is 15-20 cycles, while Cyclone is 14-19 cycles. To me this means two things: both CPUs are as deep (so the slide is not accurate), and Cyclone pipe stages are rather short which probably means frequency can be increased well beyond the current level (though probably with a too high power requirement).

Good find, link is broken.

http://www.agner.org/optimize/microarchitecture.pdf

 

[Spungo]

^ The most important slide of this.

http://www.softmachines.com/wp-cont...ines-VISCtm-Architecture-Tech-Briefing-vF.pdf

http://www.softmachines.com/wp-content/uploads/2014/10/MPR-11303.pdf

This is one of those images that looks nice in theory, but it doesn't really work in practice. Not yet anyway. If there was a way to make a single virtual core from 1000 GPU cores or 8 CPU cores, AMD and Nvidia would have done it by now. They realize this is ridiculously hard to do, so they're approaching the problem from the opposite end. Instead of making single thread code work better on multicore, make it easier to create multithreaded code. This is done by creating code libraries. AMD had their Stream project, Nvidia had CUDA. The open standard is OpenCL. Microsoft's is DirectCompute. C++ AMP is a GPU focused library for Microsoft Visual C++. Visual C# has some multithreaded libraries as well.

I'll give an example of how easy it is to create threaded software if the proper code libraries are available. Let's say I have an array of 100 numbers. I want to add 5 to every value in the array. Using current code libraries without multithreading, it would be something like this (pseudocode):

foreach (array) {
   += 5;
}

This will go through each item of the array, one at a time, and add 5.

Without a library, it's difficult to split this up to use 5 or 10 processor cores at one time. If I have a library, it's very easy:

use threading;      
foreach.threaded.threads = 10;
foreach.threaded (array) {
   +=5;
}

Now it's processing 10 at a time. Easy. Not everything can be split this easily, but it's a heck of a lot easier to do in software than it is to do in hardware.

 

[Idontcare]

Extraordinary claims require extraordinary proof.

Surely the VISC folks know this and are scrambling to get their proof into the hands of credible people who can then validate the VISC claims.

 

[Vesku]

Many cores working on the same thread, do they say if this is working on a popular instruction set such as ARM, x86, or MIPS? The design aspect is impressive if it's not running some customized instruction set designed specifically to make it easier to manage that single thread. If it's a custom instruction set then to me it downgrades from impressive to interesting. Notable that I don't see any perf/W information nor comparisons of die size.

 

[Paul98]

Many cores working on the same thread, do they say if this is working on a popular instruction set such as ARM, x86, or MIPS? The design aspect is impressive if it's not running some customized instruction set designed specifically to make it easier to manage that single thread. If it's a custom instruction set then to me it downgrades from impressive to interesting. Notable that I don't see any perf/W information nor comparisons of die size.

I thought I read that it does both ARM, and x86

 

[pw257008]

Many cores working on the same thread, do they say if this is working on a popular instruction set such as ARM, x86, or MIPS? The design aspect is impressive if it's not running some customized instruction set designed specifically to make it easier to manage that single thread. If it's a custom instruction set then to me it downgrades from impressive to interesting. Notable that I don't see any perf/W information nor comparisons of die size.

One of the articles cites the VISC folks as saying perf/W was about on par with the competing cores. Seems impressive especially for the prototype stage, assuming further improvements with refinement, if this ends up workable and the numbers end up being close to this impressive with independent testing.

 

[ElFenix]

Many cores working on the same thread, do they say if this is working on a popular instruction set such as ARM, x86, or MIPS? The design aspect is impressive if it's not running some customized instruction set designed specifically to make it easier to manage that single thread. If it's a custom instruction set then to me it downgrades from impressive to interesting. Notable that I don't see any perf/W information nor comparisons of die size.

it virtualizes the instruction set. so it can run anything.

 

[Idontcare]

Many cores working on the same thread, do they say if this is working on a popular instruction set such as ARM, x86, or MIPS? The design aspect is impressive if it's not running some customized instruction set designed specifically to make it easier to manage that single thread. If it's a custom instruction set then to me it downgrades from impressive to interesting. Notable that I don't see any perf/W information nor comparisons of die size.

Others have directly answered your question but here is the relevant passage of text, if it helps:

As you can see from the image above, there is a very specific way that they achieve this virtualized CPU architecture who’s goal is not only to abstract the cores but to also abstract the ISA, as they claim to be able to run virtually any ISA on their cores if needed, which is how they are able to demonstrate that they are running Android ICS (not Kit Kat) on their demonstration machine today at Linley.

 

[DrMrLordX]

Extraordinary claims require extraordinary proof.

Surely the VISC folks know this and are scrambling to get their proof into the hands of credible people who can then validate the VISC claims.

There's a lot of good money riding on those claims. I don't remember Bitboys having backers quite like that. Maybe my memory is just a bit hazy.

It could still be a scam, or just a good idea gone bad. Just sayin.

 

[MisterMac]

I'm skeptical that if all it tooks was a few hundred million dollars to create a way to increase IPC dramaticly - somehow even MIPS would have found a way to get it created before these guys.

Even Intel has to be researching new design ways - or experimenting with making new theorectical ISAs.

If they eventually find one they can patent and increase performance on 100%++ scale without breaking too much behind compatibility, i bet they'd do.

 

[naukkis]

it virtualizes the instruction set. so it can run anything.

So it's possible that K12/Zen is actually just one chip?

 

[sm625]

I'm skeptical that if all it tooks was a few hundred million dollars to create a way to increase IPC dramaticly - somehow even MIPS would have found a way to get it created before these guys.

Even Intel has to be researching new design ways - or experimenting with making new theorectical ISAs.

If they eventually find one they can patent and increase performance on 100%++ scale without breaking too much behind compatibility, i bet they'd do.

Dont forget that intel sat on P4 for 3 years longer than they should have. Intel only cares about its margins, profits, dividends, etc. They will not innovate unless forced.

 

[sm625]

http://www.extremetech.com/extreme/...nceptual-breakthrough-weve-been-waiting-for/2

That's all there is for performance and power I have seen. Would have expected lower power.

We got people on this thread saying this design is useless due to the 350MHz clock speed. But this image seems to negate that, no? I see no mention of any "normalization" of clock speeds. Clearly it would not perform this well at 350MHz unless IPC was an order of magnitude higher. Which means, to me anyway, that if it runs this well at 350Mhz, then it could at least conceivably scale to 3GHz, which would be totally revolutionary.

 

[Khato]

We got people on this thread saying this design is useless due to the 350MHz clock speed. But this image seems to negate that, no? I see no mention of any "normalization" of clock speeds. Clearly it would not perform this well at 350MHz unless IPC was an order of magnitude higher. Which means, to me anyway, that if it runs this well at 350Mhz, then it could at least conceivably scale to 3GHz, which would be totally revolutionary.

Eh, immediately below that performance chart the articles states that, 'Power consumption is listed as “about” the same' which isn't exactly a good sign. Does that mean that even at such a low clock frequency they still have to be running at a comparable voltage to the other designs? Which could mean that they have just as much or more total logic but are simply dividing the pipeline into less stages - that's a great way to 'improve' IPC. It also could easily mean that their 'virtualization' logic has dependencies which can't be broken up into multiple pipeline stages and hence they're limited to low frequency regardless of voltage.

Or it might be that they aren't so great at actually designing a processor and have some horrible timing paths that are killing their possible efficiency... But given their hype you'd think that they'd be loudly advertising such if it was the case since it'd result in markedly better results than what they're showing.

 

[witeken]

We got people on this thread saying this design is useless due to the 350MHz clock speed. But this image seems to negate that, no? I see no mention of any "normalization" of clock speeds. Clearly it would not perform this well at 350MHz unless IPC was an order of magnitude higher. Which means, to me anyway, that if it runs this well at 350Mhz, then it could at least conceivably scale to 3GHz, which would be totally revolutionary.

Yes, Intel must be very scared now. AMD could suddenly release a CPU with 3.5x Haswell's IPC and obliterate Intel's market share.

Eh, immediately below that performance chart the articles states that, 'Power consumption is listed as “about” the same' which isn't exactly a good sign. Does that mean that even at such a low clock frequency they still have to be running at a comparable voltage to the other designs? Which could mean that they have just as much or more total logic but are simply dividing the pipeline into less stages - that's a great way to 'improve' IPC. It also could easily mean that their 'virtualization' logic has dependencies which can't be broken up into multiple pipeline stages and hence they're limited to low frequency regardless of voltage.

Or it might be that they aren't so great at actually designing a processor and have some horrible timing paths that are killing their possible efficiency... But given their hype you'd think that they'd be loudly advertising such if it was the case since it'd result in markedly better results than what they're showing.

You should be impressed if this is true. I never hear anyone saying we'll ever get 30GHz silicon, but if you can scale this chip, which is at 0.35GHz actually faster than 1GHz Haswell, to even 2GHz, it will actually be 60% faster than Devil's Canyon, with a lot of frequency headroom left. Or is that too simplistic?

 

[Nothingness]

You should be impressed if this is true. I never hear anyone saying we'll ever get 30GHz silicon, but if you can scale this chip, which is at 0.35GHz actually faster than 1GHz Haswell, to even 2GHz, it will actually be 60% faster than Devil's Canyon, with a lot of frequency headroom left. Or is that too simplistic?

What makes you think it will scale? I am with Khato: they probably have quite large pipe stages (which would explain they only got to 350 MHz on 28 nm), and if that's correct frequency uplift will be limited.

 

[ElFenix]

So it's possible that K12/Zen is actually just one chip?

if this were k12/zen, then yes. but i very much doubt that k12/zen are this.

We got people on this thread saying this design is useless due to the 350MHz clock speed. But this image seems to negate that, no? I see no mention of any "normalization" of clock speeds. Clearly it would not perform this well at 350MHz unless IPC was an order of magnitude higher. Which means, to me anyway, that if it runs this well at 350Mhz, then it could at least conceivably scale to 3GHz, which would be totally revolutionary.

i don't know why that would necessarily be the case. you can't get a graphics card to 3GHz, and they run real well at 350MHz as well.

Eh, immediately below that performance chart the articles states that, 'Power consumption is listed as “about” the same' which isn't exactly a good sign. Does that mean that even at such a low clock frequency they still have to be running at a comparable voltage to the other designs? Which could mean that they have just as much or more total logic but are simply dividing the pipeline into less stages - that's a great way to 'improve' IPC. It also could easily mean that their 'virtualization' logic has dependencies which can't be broken up into multiple pipeline stages and hence they're limited to low frequency regardless of voltage.

Or it might be that they aren't so great at actually designing a processor and have some horrible timing paths that are killing their possible efficiency... But given their hype you'd think that they'd be loudly advertising such if it was the case since it'd result in markedly better results than what they're showing.

if that's power consumption of an experimental processor with probably limited power tuning and built out of transistors designed to minimize the rate of failures rather than other concerns, it may not be an issue.

 

[DrMrLordX]

Until we see more tests done on the demo hardware and get more information about the 80% of the die area allegedly not concerned with implementing speculative threading (or whatever it is you care to call it), it will be difficult to make any accurate comments regarding its efficiency; ability to scale to higher clockspeeds; or really anything else of substance.

One thing that seems interesting, and a bit odd, is that the provided JPEG/color compression demo that they have released would seem to indicate that there is more than just speculative threading providing an IPC boost to the prototype VISC CPU. Correct me if I am wrong, but the demo shows that two "actual" VISC cores operating as one virtual core @ real clockspeeds of 350 mhz can beat a 1 ghz Haswell core in the same task. If the speculative threading feature is 100% efficient and makes the two physical cores function as a 700 mhz virtual core, you still have a 700 mhz virtual core beating a 1 ghz Haswell core.

Or, to put it a different way, the test seems to indicate that a single "actual" VISC core @ 350mhz would beat a single 500 mhz Haswell core in JPEG/color compression.

That makes one heck of a statement with or without speculative threading. Can the VISC cores manage such a feat in other computational tasks?

 

[witeken]

What makes you think it will scale? I am with Khato: they probably have quite large pipe stages (which would explain they only got to 350 MHz on 28 nm), and if that's correct frequency uplift will be limited.

That's just an assumption. Most modern processors can go to 3-5GHz, so it seem quite extraordinary that this one can go to only 1/10th, so to me it seems you need also quite extraordinary evidence. Maybe they simply wanted to have the same power consumption as Apple A7, A15, etc.?

i don't know why that would necessarily be the case. you can't get a graphics card to 3GHz, and they run real well at 350MHz as well.

As far as I know, GPUs simply run at 1GHz because that is the best trade-off between voltage/power, performance and die area. If you reduce the clock speed to 1GHz, you can have a lot more shaders within the power budget to improve performance instead of quadratic scaling with voltage.

 

[ShintaiDK]

So it's possible that K12/Zen is actually just one chip?

Its 2 different chips. Simply shares the same socket/platform.

 

[positivedoppler]

So it's possible that K12/Zen is actually just one chip?

That is an excellent point. The fact that AMD specified they are two different chip art means neither are using VISC. If people are correct in assuming that perfectly threaded software will see no perf incr. this might noy even see the light of day