NostaSeronx
Diamond Member
- Sep 18, 2011
- 3,689
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AMD would need the GPU IP to be on the same node of the APU IP. To reduce cost and have time to market. It would be pretty bad to have to delay 20-nm APUs to the 2H of 2015. Just because someone didn't produce IP on 20-nm.
Everything collides with 20-nm being the HBM node.
GPUs have a faster design flow thus would appear much quicker than CPUs or APUs. It would be AMD's fault not to use the parts indirectly created by this guy: http://www.linkedin.com/in/atluruchaitanya
Also, if TSMC's and GlobalFoundries' HBM is only 20-nm LPM/SOC and 16/14-nm FF/FF+/LPE/LPP.
How do we explain this patent image.
Sorry for the image spam but it must be done. (16-nm SOC is a typo of 20-nm SOC)
Check the dates with;
http://www.microarch.org/micro46/files/keynote1.pdf
Ya, tell them how FP4 and SP2 are single-channel.
Everything collides with 20-nm being the HBM node.
GPUs have a faster design flow thus would appear much quicker than CPUs or APUs. It would be AMD's fault not to use the parts indirectly created by this guy: http://www.linkedin.com/in/atluruchaitanya
Also, if TSMC's and GlobalFoundries' HBM is only 20-nm LPM/SOC and 16/14-nm FF/FF+/LPE/LPP.
How do we explain this patent image.
Sorry for the image spam but it must be done. (16-nm SOC is a typo of 20-nm SOC)
Check the dates with;
http://www.microarch.org/micro46/files/keynote1.pdf
Die stacking is happening in the mainstream. It is happening now because we need it & It is going to change who and how we build sockets in the future
Ya, tell them how FP4 and SP2 are single-channel.
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