The linked PDF refers to i915g chipset with Intel GMA900, not on GMA500 (licensed by PowerVR) and used on Poulsbo and similar chipset.
Yes, but they share the same technology. And either way the point was that they're all limited to Direct3D 9 and they're not suitable for high polygon counts. Hence any form of tile based rendering is not a solution for AMD's APU scaling problem.
I really don't know, mine was a simple consideration based on the fact that if they really want to increase APUs performance without paying the die estate that Intel is going to pay with eDRAM, they need a more radical approach with reduced bandwidth needs.
I'm afraid such an approach simply doesn't exist. There's an inherent limit to temporal and spacial data access locality which dictates how much bandwidth is required. AMD is quite good at tweaking all the parameters that are involved so that a good balance between performance, cost and power consumption is achieved. There's always some room for improvement, but it's bound by the law of diminishing returns as you approach the theoretical limit. It's also not worth it to create a smaller chip if the R&D cost makes it more expensive per part, and the delay in release makes them lose sales.
Intel has a huge advantage in volume, which would justify a higher R&D cost, and yet they appear to opt for eDRAM, and I suspect the primary reason is time to market.
Also, eDRAM really doesn't add a lot of cost. Again look no further than the Xbox 360. Lastly, it affects the access latencies which means that other on-die storage can become smaller and the efficiency goes up when dealing with small tasks with dependencies between them. So it gains them several things which offset the cost.
No, they are immediate renderes w/early-z rejection, and this made a lot of difference. For example, ATI R300+ use a per-polygon tiled z-buffer approach that, while quite different that TBR, recall some of the HSR techniques used by PowerVR.
That still makes them immediate renderers. The z-pyramid has very little to do with PowerVR's technology. Geometry drawn back to front still causes overdraw. It merely speeds up the front to back approach and avoids some RAM accesses.
It's also ironic that modern graphics engines often first do a pre-z pass to eliminate shading pixels more than once. So early-z and pre-z have pretty much eliminated the need for hardware-based deferred rendering. What's happening now is that the available bandwidth is no longer wasted on overdraw but is consumed by more complex shading, higher precision, higher resolutions, etc. In fact in
Unreal Engine 4 "the majority of the GPUs FLOPS are going into general compute algorithms, rather than the traditional graphics pipeline"!
Graphics is quickly evolving toward software-oriented approaches. So AMD is losing its grip on the rendering process. Hence implementing the most advanced hardware TBDR on the planet wouldn't help much. Looking at GCN, they clearly understand this. And it also means there's no substitute for bandwidth other than big caches.