From a VLSI perspective, when designing a chip on a new process node, there are a few things you have to do:
1. Redesign all your standard gates for the new process node (each node shrink has slightly different rules about the spacing of wires, silicon, and vias for the various silicon/metal layers), and make sure these work and are as fast as you expect.
2. Redesign all your by-hand-laid-out components like cache cells/lines, buffers, and other regular structures for the new node's rules, and make sure these all work at the speed you expect.
3. Synthesize all of the components that need to be synthesized, and see if it works at the speed you expect. If it doesn't, change the input parameters to the synthesis until it does.
4. Put everything together into one die, including the clock tree, and see if this all works together at the speed you expect. If it doesn't, back up to the step where you screwed up and try again.
Given all that, it doesn't really matter *that much* from a VLSI transistor/wire layout perspective whether you're using an old or new design on a new process node. An old design is slightly better because all of the engineers are more comfortable with what the expected/ideal behavior is going to be, but both old and new designs need to jump through all the same hoops to reach a final design.