The specific reason for the cache change on SL-X had to do with the adoption of a the Mesh vs. Ring Bus. Since the don't do per core L3 slices like AMD, all of their cores had the same 100ms+ latency to L3. Increasing the L2 reduced the dependency on L3 performance.
It's doubtful if a 8c socket 1151 CFL compatible die exists that it would be based off server die. I personally question the existence of a 8c CFL altogether, but assuming it exists it would still be ring bus and therefore not have the alterations made with SL-X.