Does AMD's implementation even allow the igp to use L2?
People mentioned Iris Pro, but Iris Pro is not only on the R versions, its also on the mobile versions, actually they are the same thing with diferent clocks, turbos and TDP windows.
That Brix where able to use R version on these things is kinda suprissing, and they are getting named because of these, we have benchmarks.
Them you decided to go and compare it to a 7850K, and... hang on a minute, i remember you telling me in my face that i cant compare the 5350 to a G1820... ok.
Will be a nice increase for integrated GPU even if it's not as good as having an eDRAM cache.
50+% FPS gains in Linux going from DDR3-1333 to DDR3-2133.
http://www.phoronix.com/scan.php?page=article&item=amd_kaveri_memory&num=2
Granted will be a bit disappointing if lowest end DDR4 in notebooks isn't at least DDR4-1866. JEDEC spec has a DDR4-1600 speed bin but hopefully that will only be seen in phones and tablets.
Chip architecture can also help, as Maxwell shows: in the mobile field the DDR3 equipped 850M beats 750M by as much as 80%. Sure it's a bigger chip, but it still shows what can be done using the same cheap DDR3 as the last generation.Dont get me wrong, it will be a great increase compared to today. But the IGP will suffer the same if not even higher bottleneck than today without something else as well.
Chip architecture can also help, as Maxwell shows: in the mobile field the DDR3 equipped 850M beats 750M by as much as 80%. Sure it's a bigger chip, but it still shows what can be done using the same cheap DDR3 as the last generation.
Maxwell probably has larger GPU caches.
Cache size is only half of the story, what you do with that cache is also important.Indeed. GM107 has 2MB L2, GK107 "only" has 256KB. So that's 8x the on-chip cache right there.
Cache size is only half of the story, what you do with that cache is also important.
All this makes me think I should read more about how Intel and AMD make use of their cache structure in Haswell and Kaveri. I know Haswell GPU makes use of L3 cache, but know little about Kaveri from this point of view.
Of course. I thought that went without saying. But still, adding that much extra cache is bound to have an effect.
Trinity/Richland/Kaveri/Kabini's GPU doesn't use the CPUs L2. The IGP is connected directly to the northbridge/memory controller by a dedicated bus.
I assume there still a GPU L2 like any other GCN CU array?
I wonder if APUs could benefit from perhaps shrinking the CPU L2 and add a larger L3 shared with the GPU? Considering how much performance Nvidia has been able to extract with the 2MB L2 of the GM107, despite the "low" memory bandwidth available, I'm wondering if AMDs APUs would benefit from a larger L2 cache given how much they're constrained by memory bandwidth...?
That would further erode the CPU performance, because AMD L2 cache is already slow. Moving everything else to L3 and sharing it with a big iGPU would certainly assure that most CPU workloads are sure to go to the main memory.
I wonder if APUs could benefit from perhaps shrinking the CPU L2 and add a larger L3 shared with the GPU? Considering how much performance Nvidia has been able to extract with the 2MB L2 of the GM107, despite the "low" memory bandwidth available, I'm wondering if AMDs APUs would benefit from a larger L2 cache given how much they're constrained by memory bandwidth...?
I'm not sure that's the case. Firstly, I didn't say "remove" the CPU L2 cache, just reducing its size a bit. Intel's CPUs since Nehalem have gotten along just fine with 256KB L2. AMD's L1 cache is also pretty big on Kaveri (192KB), so I don't think it'll have too much influence on CPU performance. Secondly, the above assumes that you're running both CPU and GPU heavy applications simultaneously. Thirdly to make room for the additional cache, you could cut the number of CUs, f.x. from 8 to 6. You loose a bit of raw computing power, but the additional performance from the big "fast" (faster then main memory anyway) L2 would properly offset that.
I do agree on that AMD's memory controller could do with an upgrade though.
I haven't been able to dig up anything solid on that, but I have a strong suspicion that's the case.
I wonder if APUs could benefit from perhaps shrinking the CPU L2 and add a larger L3 shared with the GPU? Considering how much performance Nvidia has been able to extract with the 2MB L2 of the GM107, despite the "low" memory bandwidth available, I'm wondering if AMDs APUs would benefit from a larger L2 cache given how much they're constrained by memory bandwidth...?
Cape Verde has an 512KB of L2 cache, 256KB per memory controller. AMD seems to be increasing it's cache size for GCN, from 64 > 128 > 256KB pe memory controller.The GPU cores have 16KB of L1 cache. They have access to the CPU L2 cache when running HSA workloads (which of course don't exist yet)
no there is L2, it is needed it maintains coherency and it where all the L1's write two, its better to think of it as memory controllers are tied to cache, not the other way around,Since the L2 cache is tied to the memory controller, I should have figured Kaveri's iGPU would have none.