Agreed, III-V + GAA will be a massive change that is likely to drive higher frequencies, and therefore performance. I like to think of each node (irrespective of uArch changes) as a step ladder with new improvements in process design have larger leaps than just scaling down.
Lately, the advancements have been compounding. Prior to strained silicon, the only knob you could turn to boost transistor performance was to shrink them. That stopped working. However, there have been so many more dials added. Strained silicon came first, then HKMG, then transistor "shaping."
Now, you improve a little on the strain, and a little on the dielectric, and a little on the transistor design... and you get a pretty big boost.
14nm is probably going to be the biggest improvement Intel has had in quite some time. The density is more than doubling (2.2x or so), the performance and power improvements will be above average. Intel's claims for their 45nm process were "~30% reduction in transistor switching power" and ">20% improvement in transistor switching speed" over their 65nm process. Intel's numbers for their 14nm process are 67% reduced power and 40% increased performance over 22nm.
This is all contingent on whether or not Intel's telling the truth, or cherry picking of course, but thus far they've been fairly honest, from my perspective. I'm still stumped as to what miracles they've managed to work to make these breakthroughs, but they're insistent on keeping quiet.
Also, for any of these claims I'm making, I can provide upon request. For direct quotes, just copy paste the quote into google and click the first PDF you find.
One last bit: the "post-silicon era"
is coming. Applied materials stated last June that the likely introduction for SiGe would be at the 10nm or 7nm node, and Imec has stated 10nm as well as of this January, and I think this isn't Intel exclusive. Idontcare probably is legally bound not to comment on that, though