Sorry for the drop in output. Had a huge switch up in hardware, had to sell a bunch of processors to pay some hardware changes. My monthly budget for power remains the same though, so I've increased the clock speeds on existing CPUs to attempt to offset the reduction in cores. D:
48x Zen2 + 16 Zen+ cores have been replaced by 32 Zen3 + 12x Zen2 (though some of these aren't full time anymore, server stuff, "gaming" etc)
Science has to be done.
Interesting tidbits: looking at AMD's Zen core performance counters (via a custom software tool a friend made) current WCG WUs (MCM, formerly MIP and OPN appear to be very high-IPC throughput workloads that reside almost entirely in the L3 cache on Zen2 and 3. I can get some numbers later, but from what I was seeing; 5950X is reporting a 90%+ L3 cache hitrate with an 80%+ uOp Cache Hitrate, and the backend is tracking up to 4 instructions retired per clock at ~4.3 GHz, per core, with SMT. That's 2 / thread, which is extremely high for a CPU workload. The high uOp$ Hit rate is why that's possible, since the front end is dispatching from the wider op cache rather than decode, it's also more efficient and apparently these workloads scale really well to Zen2/3 with the big internal caches. The "disappointing news" is that V-cache equipped processors of the next-gen Zen3 refresh might not yield large gains for workloads already mostly in L3 cache, though a full load of ARPs would probably see a lot of benefit from that.
My final note is, I have laid my filthy, tech-obsessed paws on an RTX 3090 which I want to put to work in Folding At Home. So if I could join the Anandtech FAH team, I can see what it can do, if you'd have me? (I also have a TITAN Xp available). Meow.