What capabilities MUST a CPU possess?

[chrstrbrts]

Hello,

What capabilities must a CPU have so that a computer can effectively implement software?

I compare CPUs to cars. Cars have a ton of bells and whistles: power locks, AC, power windows, etc. But you don't really need any of those things.

However, if you strip away enough things, eventually a car will cease to be a car. That is, there is a basic criteria a car needs to function and meet the definition an automobile.

So, what about CPUs? I think that there is a trend now to move software "on chip" and have CPUs and microprocessors do things that were previously within the realm of software.

But what "atomic" operations must exist on a CPU so that you can run software?

My layman's guess is that the CPU must have the ability to add in binary and make branch decisions.

What are your thoughts?

 

[NTMBK]

Integer add, subtract and bitshift (multiply can be implemented by combining those). Memory load and store. Jump.

 

[chrstrbrts]

Integer add, subtract and bitshift (multiply can be implemented by combining those). Memory load and store. Jump.

Thanks, but how would you implement branching (if statements and such) with the atomics you've mentioned?

 

[Borkil]

5 stages

Instruction Fetch - CPU needs to know what instruction it is doing and what the next instruction is (Program counter)

Decode - CPU needs to understand what the instruction is and what steps it needs to take do execute it

Execute - Actually execute the instruction

Memory - Needs to have the ability to save results. (otherwise what's the point?)

Writeback - Saves the results into registers. Writeback is not "necessary" but using only memory is super slow.

http://en.wikipedia.org/wiki/Classic_RISC_pipeline

 

[serpretetsky]

Central processors should genrally be touring complete.
http://en.wikipedia.org/wiki/Turing_completeness

NTMBK got the basic ones down. I think you are right, OP, in that you would also need to add a conditional jumping mechanism to that (not 100% sure about that).

However, there are far far more minimlistic touring complete instruction sets:
http://en.wikipedia.org/wiki/One_instruction_set_computer

5 stages

Instruction Fetch - CPU needs to know what instruction it is doing and what the next instruction is (Program counter)

Decode - CPU needs to understand what the instruction is and what steps it needs to take do execute it

Execute - Actually execute the instruction

Memory - Needs to have the ability to save results. (otherwise what's the point?)

Writeback - Saves the results into registers. Writeback is not "necessary" but using only memory is super slow.

http://en.wikipedia.org/wiki/Classic_RISC_pipeline

That really doesn't define the essence of a processor or a computer. That is a typical simplified architecture that we use.

 

[janeuner]

It must have frivolous characteristics which attract irrational fanboys.

 

[Borkil]

Central processors should genrally be touring complete.
http://en.wikipedia.org/wiki/Turing_completeness

NTMBK got the basic ones down. I think you are right, OP, in that you would also need to add a conditional jumping mechanism to that (not 100% sure about that).

However, there are far far more minimlistic touring complete instruction sets:
http://en.wikipedia.org/wiki/One_instruction_set_computer



That really doesn't define the essence of a processor or a computer. That is a typical simplified architecture that we use.

But those are the abstract things that a cpu needs to be able to do. Without any one of those stages it won't be able to perform useful work. "Turing machines are not intended to model computers, but rather they are intended to model computation itself." from http://en.wikipedia.org/wiki/Turing_machine

NTMBK described functions that the execute stage needs to perform. Which is getting into the nitty gritty of the "engine" of the car.

 

[serpretetsky]

But those are the abstract things that a cpu needs to be able to do. Without any one of those stages it won't be able to perform useful work.

I will agree with you that some of those stages really are necessary for the idea of a computer, but not all 5.

1) A computer needs to be able to accept and decode instructions from a user
2) A computer needs to be able to execute those instructions
3) A computer needs to be able to store the results in some sort of memory to give the result back to the user or continue executing more instructions on the data.

"Turing machines are not intended to model computers, but rather they are intended to model computation itself." from http://en.wikipedia.org/wiki/Turing_machine

that is true. However, I never specifically mentioned turing machines. I referred to turing completeness. Basically, any turing complete computer can perform the same computations that any other turing complete computer can. This includes, by the way, the turing machine. Most micropressors and all microcontrollers (i think?) are turing complete. GPU's only became turing complete recently with more advanced shaders.

NTMBK described functions that the execute stage needs to perform. Which is getting into the nitty gritty of the "engine" of the car.

I would argue the exact opposite. A programmer only cares about the instructions a CPU can execute. He really doesn't care that underneath the hood there are 5 stages. There could be 2 stages or 2000000 stages and it would make no difference to the programmer. He wants to make sure that the processor performs well, sure, but he doesn't really care HOW that is accomplished.

What you are describing, the 5 stages of a typical RISC architecture, is the engine under the hood. The instructions are the control mechanisms that the driver has access to. They define what functionality the programmer has access to and how he can control the mechanism.

 

[KWiklund]

Thanks, but how would you implement branching (if statements and such) with the atomics you've mentioned?

You need a Program Status Register, which contains assorted status bits that may be used for branching (various arithmetic operations may cause these to be set of cleared). The conditional jump instruction determines whether or not to change the value of the program counter (PC) register based on the value of the corresponding status bit. The PC register contains the address of the next instruction. Under normal operation, it simply increments after each instruction is read. Loading it with a different address though will cause the program to "jump" to that address.

 

[Cerb]

http://en.wikipedia.org/wiki/Zero_instruction_set_computer
http://en.wikipedia.org/wiki/One_instruction_set_computer
Let's end all the instruction and pipeline issues right here .

As mentioned already, it can be determined by Turing completeness. Generally, hardware processors are not considered incomplete due to limited memory space, since peripheral IO features allow for very large data ranges to be handled, so long as enough of the intermediate value can be stored in the processor's own memory to keep processing (FI, a "places" offset, two current, "digits," and underflow/overflow/carry data, would be almost enough).