good work!I successful package your EFI file into the bios,my CPU 0.2GHz higher than the old one.CB R15 scores reached 2950,frome 2800 to 2950.Thank you.
I successful package your EFI file into the bios,my CPU 0.2GHz higher than the old one.CB R15 scores reached 2950,frome 2800 to 2950.Thank you.
I have uploaded version 3407 here.@kjboughton
I have tried to message you, but i cant, can you help me with the BIOS of my Z10pe-d8ws? Thank you!!!!!!!!
convert V3x2_50_vcc.EFI to FFS
if i put v3.efi into clean bios (no haswell microcodes), do i need to do any modification on Windows?
if i put v3.efi into clean bios (no haswell microcodes), do i need to do any modification on Windows?
On Asrock X99 Overclock Formula work great.https://peine-braun.net/public_files/v3_payne_70_50.efi
You are welcome.
Any other voltages are a matter of seconds to compile.
Now I am working on multi-cpu support. V3x2 source would really help.
I have the source of the V3x2,do you need it?That probably wont work... for me all V3x2 cannot be included for some reason... BIOS wont post.
Not Sure why... thats why I have been asking for the source a few times. Maybe its issues with the C compiler, or it is related to SMP functions. I am trying to find out.
I have uploaded some more undervolting core/cache voltage driver combos, also including the .ffs already:
https://peine-braun.net/public_files/XEON_V3_BIOS_MODS/EFI-Drivers/
Enjoy.
Use UEFITOOL to add .ffs files directly to BIOS after finding out your silicon luck with .efi
I have the source of the V3x2,do you need it?
@CANONKONG YES!
A list of tool and steps necessary to compile would be helpful as well!
#include <Uefi.h>
#include <Library/UefiLib.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PrintLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Protocol/SimpleTextOut.h>
#include <Protocol/MpService.h>
EFI_MP_SERVICES_PROTOCOL *mpp = NULL;
UINT32 unlock_status = 0;
VOID EFIAPI unlock(IN OUT VOID* Buffer)
{
UINT32 EAX;
AsmCpuid(0x0001, &EAX, NULL, NULL, NULL);
if (EAX != 0x306F2)
{
unlock_status = 1;
return;
}
UINT64 edx_m = 0xFFFFFFFF00000000ULL;
// UINT64 eax_m = 0x00000000FFFFFFFFULL;
UINT64 eax14_m = 0x0000000000100000ULL;
UINT64 dl_m = 0x000000FF00000000ULL;
UINT64 al_m = 0x00000000000000FFULL;
UINT64 v1, v2;
UINT64 rm;
rm = AsmReadMsr64(0x8B);
if ((rm & edx_m) != 0)
{
unlock_status = 2;
return;
}
rm = AsmReadMsr64(0x194);
if ((rm & eax14_m) != 0)
{
unlock_status = 3;
return;
}
AsmWriteMsr64(0x150, 0x8000000100000000ULL);
rm = AsmReadMsr64(0x150);
if ((rm & dl_m) != 0)
{
unlock_status = 4;
return;
}
v1 = rm & al_m;
AsmWriteMsr64(0x150, 0x8000020100000000ULL);
rm = AsmReadMsr64(0x150);
if ((rm & dl_m) != 0)
{
unlock_status = 5;
return;
}
v2 = rm & al_m;
AsmWriteMsr64(0x150, 0x80000011FD600000ULL | v1);
rm = AsmReadMsr64(0x150);
if ((rm & dl_m) != 0)
{
unlock_status = 6;
return;
}
AsmWriteMsr64(0x150, 0x80000211FD600000ULL | v2);
rm = AsmReadMsr64(0x150);
if ((rm & dl_m) != 0)
{
unlock_status = 7;
return;
}
UINT64 mvr = v1 | (v1 << 8) | (v1 << 16) | (v1 << 24) | (v1 << 32) | (v1 << 40) | (v1 << 48) | (v1 << 56);
AsmWriteMsr64(0x1AD, mvr);
AsmWriteMsr64(0x1AE, mvr);
mvr = mvr | 0x8000000000000000ULL;
AsmWriteMsr64(0x1AF, mvr);
rm = AsmReadMsr64(0x620);
rm = (rm & 0xFFFFFFFFFFFF0000) | (v2) | (v2 << 8);
AsmWriteMsr64(0x620, rm);
rm = AsmReadMsr64(0x194);
rm = rm | eax14_m;
AsmWriteMsr64(0x194,rm);
//UnicodeSPrint(msg, sizeof(msg), L"CPUID %8X\n", EAX);
//Print(msg);
/*
UINTN apn;
CHAR16 msg[16];
mpp->WhoAmI(mpp, &apn);
UnicodeSPrint(msg, sizeof(msg), L"CPU #%03x\n", apn);
Print(msg);
// Print(L"Hello world.\n");
*/
}
VOID PrintStatus(IN UINTN pknum)
{
CHAR16 msg[16];
UnicodeSPrint(msg, sizeof(msg), L"V3 CPU_%2X ", pknum);
Print(msg);
switch (unlock_status)
{
case 0:
Print(L"All Turbo set.\n");
break;
case 1:
Print(L"Wrong CPU.\n");
break;
case 2:
Print(L"MicroCode present.\n");
break;
case 3:
Print(L"Error:0x194.14\n");
break;
case 4:
Print(L"Error:0x150.1\n");
break;
case 5:
Print(L"Error:0x150.201\n");
break;
case 6:
Print(L"Error:0x150.11\n");
break;
case 7:
Print(L"Error:0x150.211\n");
break;
}
}
EFI_STATUS EFIAPI V3x2Entry (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
gBS->LocateProtocol(&gEfiMpServiceProtocolGuid, NULL, (VOID**)&mpp);
UINTN cores_num;
UINTN cores_enum;
mpp->GetNumberOfProcessors(mpp, &cores_num, &cores_enum);
/*
// CHECK
EAX = 1
check_cpu_id EAX == 0x306F2 // Wrong CPU
READ MSR 0x8B: EDX == 0x0 // MicroCode Present
READ MSR 0x194: EAX.0x14 == 0 // OverClocking Locked
// WRITE
WRITE MSR 0x150 EDX:0x80000001 EAX:00000000
READ MSR 0x150 dl == 0 // MailBox Error
AL->Var1
WRITE MSR 0x150 EDX : 0x80000201 EAX : 00000000
READ MSR 0x150 dl == 0 // MailBox Error
AL->Var2
WRITE MSR 0x150 EDX : 0x80000011 EAX : 0xFD600000 + Var1
READ MSR 0x150 dl == 0 // MailBox Error
WRITE MSR 0x150 EDX : 0x80000211 EAX : 0xFD600000 + Var2
READ MSR 0x150 dl == 0 // MailBox Error
WRITE MSR 0x1AD Var1 to each byte EDX and EAX
WRITE MSR 0x1AE Var1 to each byte EDX and EAX
WRITE MSR 0x1AF Var1 to each byte EDX and EAX, EDX = EDX or 0x80000000
READ MSR 0x620
Var2 -> AL
Var2 -> AH
WRITE MSR 0x620
READ MSR 0x194
Check ? EAX.0x14
SET EAX.0x14
WRITE MSR 0x194
// All Turbo Set
*/
CHAR16 msg[256];
UnicodeSPrint(msg, sizeof(msg), L"Cores:%3x, enabled:%3x\n", cores_num, cores_enum);
// Print(msg);I have the source of the V3x2,do you need it?
...
The 2 CPU's above, are first E5-2679v4, the fastest LGA2011v3 CPU (20cores all turbo at 3,2Ghz stock), and above are my old two Haswell-E enginnering samples. They are two 12 cores 30MB L3, run at 3,1Ghz full load (the turbo is only to 32x and has to be disabled with Cstates otherwise they are unstable those are old samples), but at the same time these do not have any AVX delta, aka run 31x even in full AVX load. And this works fine and uncore does not throttle. These use some ancient microcode with TSX enabled but there definitely is a microcode cause there are no uncore issues.
Now, this brings to me an idea. The 2696v3 can either be ran without microcode and C-states so there is no AVX underclock, but the uncore throttles down, or with C-states enabled so uncore is fine and the CPU generally performs better out of AVX. But the thing is, the 12 core ES could do both. But I was not able to find anywhere on the internet a valid uncore of that kind. Aka pre-launch uncore with TSX and no uncore throttle, no AVX throttle.
If you go to Asrock X99 extreme 4:
http://www.asrock.com/mb/Intel/X99 Extreme4/?cat=Download&os=BIOS
The very first bios 1.2 uses the old TSX microcode even for retail Haswells. The bios also has the 2 microcodes for the engineering samples. These would be amazing if someone was able to extract them or find them somewhere so we could use them. I'm not skilled enough to extract them from the bios. And I was unable to find them. The first microcode Intel released for Haswell-E is already post launch with all the errata fixes.
ASUS&GIGABYTE can use a bios delete the microcode and set all the settings in the BIOS(set max turbo radio,CoreVOffset -70mv & CacheVOffset -50mv) and it worked higher frequency
very well without a EFI driver.
Stepping 1 v3 Xeons (ES) can use V3-1.FFS. I have test v4 Xeons，it worked with change the MSR.CANONKONG, do you think this is possible with stepping 1 v3 Xeons (ES) and with v4 Xeons??
Does this hack of yours still require a bug in CPU microcode?
The link u posted is 404 now... Could u re-upload it for us? Thx!This same microcode (0x1F / rev 31) was in ASUS Z10PE-D8 WS BIOS release 0301 (initial).
I have extracted the raw binary and converted to to comma delimited ASCII for use with VMWare CPU Microcode Update Driver for Windows.
right click and save link as here...