P.S. According to this article Vega 10 will have a TDP of 225W (@ 1465 Mhz clock) That TDP is too high for a laptop, but it does have the capability for 16GB of HBM2 (which I think would be enough for shared system RAM in a laptop) and I suspect the TDP could drop low enough with downclocking particularly with some functional units disabled (ie, harvested version of Vega 10).
IDK. It seems like that have and IMC deficiency even when both controller are working.
A rumor that an HBM-powered APU was in the works was reported on by Fudzilla in March 2015. The chip would combine 16 Zen cores (up to two threads per core) with a large “Greenland” (now “Vega 10”) GPU. The processor would be hooked up to a 16 GB HBM device via a silicon interposer, and deliver 512 GB/second of memory bandwidth to the APU compute units. Four channels of DDR4 memory would also be included, supporting a maximum capacity of 1 TB. Although those specs clearly point it toward HPC and other high-end server work, such a design could be scaled down to AMD’s desktop and laptop markets as well.
Well, if we look at the Fury Nano, it was a 175w tdp part, 100w less than a fury X. With a node shrink since then AMD could release a much lower tdp Vega for laptops, and eventually a nice Ryzen HBM APU would be great.
That 175W is 64% of the 275W starting point.
So if we started at 225W (Full size reference clocked Vega 10) and applied 64% that would give us 144W for a full size downclocked Vega 10. Assuming the downclocked Vega 10 was also reduced 20% in size by disabling units that would result in a TDP of 115.2W. (I think that would work as the current dGPU (GTX 1060 6GB) in the 2017 Razor Blade (14") is rated at 120W when used on the desktop.)
make them into keychains
IDK. It seems like they have an IMC deficiency even when both controller are working.
A Ryzen APU with +/- 50w CPU & 100w Vega GPU would definitely be possible medium term IMHO. That would be a powerhouse combo, and something to maybe even grab Apple's attention. Hopefully AMD now has enough resources available with now both Ryzen & Scorpio both being out of R&D. Looks like Vega was the project which got the short end of the stick with all the projects they had going on.
Could AMD make a APU out of the die by using a GPU with a HBM controller MCM? (And use HBM2 or low cost HBM for system RAM)
I wonder if they could use four dies with one broken memory controller each for X399?
This with 6 cores per die for a 24C/48T quad channel processor?
Or does each CCX need to have its own memory controller?
I wonder if they could use four dies with one broken memory controller each for X399?
This with 6 cores per die for a 24C/48T quad channel processor?
Or does each CCX need to have its own memory controller?
Not so much it's only memory controller but each mem controller has very specific pins that go to specific memory slots. It would be really awkward trying to figure out which memory slots on your server are the correct ones you should be installing memory into.
The Servers do have octa channel.....but X399 is quad channel:
http://www.tweaktown.com/news/57772/asrock-x399-taichi-ready-amd-threadripper-16c-32t/index.html
So all the DIMM slots should be functional assuming a four die (each with 1 memory controller) arrangement works. (memory controller on each die is routed to the right pins on the processor PCB)