then explain bulldozer ES's.Bottom line is that if AMD's Zen could hit Intel-like frequencies they would have pushed their Zen ES to match Broadwell-E base clock in their Blender demo rather than nerf the Broadwell to make their point.
Stilt also says current Summit Ridge ES chips are shipping at 2.8ghz base and 3.2ghz Max single core turbo. Max single core turbo on BDW-E is 4GHz.
then explain bulldozer ES's.
Remember you have in BDW-E a already know core, an already known cache sytsem and uncore. Compared to a complete new core being brought up for the first time, a new cache system being brought up for the first time and a new uncore being brought up for the first time.
They are in no way comparable.
Also clock/power scaling and Fmax can be two very different things.
so AMD's ES history doesn't agree with you
what we know of the architecture doesn't agree with you
so how are you determining clock speeds again?
Can't wait until the final silicon is out and we'll see who winds up right.
I wouldn't even try to guess Fmax at this point what makes you so sure other then Derp Derp AMD?
And at this point you have no ability to justify your position from a technical perspective, I have no idea what clocks will look like, what we can say is that there is nothing obvious from the information that we have that say Zen will clock lower then CON.
The only real information that we have is that EX has higher IPC and lower top clocks then PD and that there are quite a number of locked models as well...And at this point you have no ability to justify your position from a technical perspective, I have no idea what clocks will look like, what we can say is that there is nothing obvious from the information that we have that say Zen will clock lower then CON.
thats complete bull,The only real information that we have is that EX has higher IPC and lower top clocks then PD and that there are quite a number of locked models as well...
So a Zen ES running @3ghz doing a throughput workload is now targeting low TDP and clocking "LOW". Ignoring that AMD have said released products will be higher clocked. Remember 8 core BD at this stage was clocking @2.8ghz........AMD is trying to turn things around by showing efficient CPUs at low TDP.
If you project that only piece of real information to ZEN it does not look well,even lower clocks and even more locked CPUs...
Yup on the technical front there is zero info so anything anybody says is speculation,so stop sounding like a brocken clock by attacking anybody who says anything negative about AMD/ZEN.
Remember 8 core BD at this stage was clocking @2.8ghz........
Well from what i remember it was more around 7 months from those leaks until release (march'ish to October) .Are you expecting Zeppelin to release in Q3 2017?
Well from what i remember it was more around 7 months from those leaks until release (march'ish to October) .
We saw Zen running @3ghz over a month ago and now the release date is supposed to be in Q1. So if it launches march its 7months , if it launches jan its 5. BD birth wasn't exactly smooth sailing, Zen appears to be much happier.
If you go back to when people like Thevenin (semiaccurate) Neilz (beyond3d) saw Zen it will be ~1 year.
Yeah we have a lot of theoretical info,but ZERO info on how it's implemented ZERO real measurements,ZEN at launch might be clocked at 5Ghz or at 2.8Ghz anything we do is just speculation.So now your showing your bias, all i want is a technical reason for a position, when you have a technical position it can then be discussed and we can all learn something. I dont care if your negative, wouldn't i by your logic be attacking Slilt insistently, oh look im not ..... funny that.........
The average IPC improvement over PD should be 15.5% (according to AMD) and that's quite close to the actual average. However there are also MANY cases where Excavator performs the same or even worse than Piledriver. Still far from "smashing", even if it was always 15.5% faster IMO.
Jim Keller is just one man.
Yeah due the doubled L1D and slightly faster L2, not due the IPC itself. The same way Skylake, which performs ~129% better than Piledriver in SuperPI doesn't have even remotely that much higher IPC in extremely legacy workloads (which SuperPI is).If you look at cases like SuperPi or wprime, XV's lead over PD is staggering. Clearly the potential is there, whether it's potential for XV to succeed or for PD to fail (miserably).
The more results I see from XV, the more I realize that it's all over the damn map.
Yeah due the doubled L1D and slightly faster L2, not due the IPC itself. The same way Skylake, which performs ~129% better than Piledriver in SuperPI doesn't have even remotely that much higher IPC in extremely legacy workloads (which SuperPI is).
It helps if you view it as a quad core for integer workloads, and a dual core for FP. Essentially the module design at work.
My 845 can actually match my old 920 in integer, but fails miserably at anything resembling FP.
It's certainly not "as fast as Piledriver/Vishera" though.
Yeah due the doubled L1D and slightly faster L2, not due the IPC itself. The same way Skylake, which performs ~129% better than Piledriver in SuperPI doesn't have even remotely that much higher IPC in extremely legacy workloads (which SuperPI is).
Yeah I would love for AMD to do the same,for the exact same reasons.Dude, you are showing colors.
IPC without respect to L1 or L2 or ?
Please define your labaratory standars for defining "IPC". - You know, so we can measure them.
-"Facts without data is dreams." - quote cytg
Dude, you are showing colors.
IPC without respect to L1 or L2 or ?
Please define your labaratory standars for defining "IPC". - You know, so we can measure them.
-"Facts without data is dreams." - quote cytg