Does anybody have any solid information (links?) on the technical details of DDR-II? A lot of people have been posting conflicting rumors:
- DDR or QDR?
- bandwidth?
- serial or parallel bus?
- SRAM row caches?
I went to Jedec's website, and the best I could find was this probably out-of-date PDF. Much of the design nature seems unresolved (at the time of writing), but it does imply that DDR-II will have a parallel bus (pg. 3: parallel control offers lowest inherent latency, DDR-I backwards compatibility).
Is there any more current information out there?
- DDR or QDR?
- bandwidth?
- serial or parallel bus?
- SRAM row caches?
I went to Jedec's website, and the best I could find was this probably out-of-date PDF. Much of the design nature seems unresolved (at the time of writing), but it does imply that DDR-II will have a parallel bus (pg. 3: parallel control offers lowest inherent latency, DDR-I backwards compatibility).
Is there any more current information out there?