AMD has removed Mendocino (client) and (chromebook) from being Entry-Level. This type of removal in general means another product is in the pipe.
Zen1 is available in the 2023-2025 product portfolios. Which with a high confidence would be a variant with an energy-efficency focus.
However, it should be looked at as if it is Zen(14LPP) -> Zen+(12LP) -> Zen1[e](12FDX). The 12FDX NPI/yield/integration team at GloFo has been contracted by AMD. So, it is likely the new node selected is 12FDX. Current WSA has a fixed cost for 14nm/12nm. If 12FDX is the thing, 2H'23~end of 3H'23(WSA-timeframe) should see a revision/refresh of the WSA for 2024~2028 timeframe. With 12FDX getting a decreasing cost ceiling through that time period. Leading to 2024 product price being based on 2025 wafer costs, and 2025 product price being based on 2026 wafer costs.
"Zen" vs "Zen1"
| Zen | Zen1 |
Standard Libs: | 10.5T/9T | 6T < xT < 7.5T |
Macro Count: | 20 Macros | sub-10 Macros |
Spectre Fixes? | No(already taped out) | Yes |
New FPU? | No | Yes (Gracemont ISA compatibility) |
L3 in CCX? or Fabric? | CCX | In-Fabric as SLC |
Performance or Energy-Efficient | Performance Core | Energy-Efficient Core |
Zen1 should have back-ports from Zen4/Zen5. The FPU will likely be from Zen4. Rather than Zen2 Mendocino's (256-bit MUL+256-bit ADD, removing the later two FP pipes from Renoir/other Zen2s). With Zen1's FPU doing this, which allows Zen1 to get VEX-encoded AVX512 instructions like Gracemont/Crestmont/Etcmont:
(note VNNI/IFMA)
L2 should fallback on Jaguar/Mongoose-esque shared L2.
I can say with high confidence that while it might be on AM4, it will not be backwards compatible. It should be on a socket similar to AM4e, which is the 64-bit DIMM/SO-DIMM concept for Stoney-AM4/Concept Raven2(when it had 64-bit memory)-AM4. It should be on leading/bleeding edge memory solution, thus be a 64-bit dual-channel (x32/x32) CAMM solution. Where, it can later fit into FT6b/FT7 for Notebook/Chromebook CAMM as well.
Example AM4(current) -> AM4e(same socket, breaks compatibility);
JEDEC and vendors like ADATA? is focusing on 64-bit CAMMs.
AM1 was suppose to be succeeded by essential-variant of AM4.
Only sure about these:
Zen1 E-core SoC's "WHL, Crest" => Essential-base for AM4e SoC
Mendocino's successor SoCs,
Zen4 E-core SoC "PHX3, Valley" => Mainstream AM4e SoC (Upsell Option)
Zen5or4 E-core SoC "STX3, Valley" => Mainstream AM4e SoC (Upsell Option)
These will be the cheapest AM4 options in the extra extended AM4 lifespan. From what I can find Crest = CPU-orientated (More CPU cores, Less GPU cores) and Valley = APU-orientated (More GPU cores, Less CPU cores). Crest is similar to Summit/Pinnacle => the top of a wave and Valley(another name of trough) => bottom part of a wave. This naming scheme is exclusive to these cost-optimized solutions.