If you look back at Intel's uarch history they introduced a totally new one about every four years, up until Netburst. The reason that this was warranted is because they were incorporating industry proven technologies each time, which were previously held back by transistor budget (back when most of them were spent on pure logic and not cache and buffers). This was a trickle down effect where the desktop CPUs were catching up with more expensive server/workstation CPUs. I believe that Intel basically hit the apex of basic CPU technology improvements with P6, where they implemented a 3-wide superscalar OoOE processor with RISC-like execution engine. It's about at this point where Intel started really getting competitive in performance with traditional RISC CPUs.
With Netburst they didn't have that much big industry knowledge to tap into and instead moved into risky new experimental techniques. These would all perform well only if certain conditions were met. The long pipeline would perform well if the improved branch prediction was generally sufficient enough. The slow decode path would perform well if the trace cache had a sufficient hit rate. The tiny L1 dcache would perform well if the improved load to use latency offset the lower capacity. The double pumped ALUs would perform well if code avoided instructions not handled by them like shifts. So on and so forth. Of course it goes without saying that they also bet on eventually reaching a higher clock speed than they'd be able to. But it's all part of a common theme, the part had a ton of gambles.
Most of these things proved to not be true enough of the time and made for poor tradeoffs. Although you don't hear about it much the cost of missed R&D must have been immense.
Intel realized that at this point it makes more sense to stick with what works and incrementally refine it in safe ways that yield more predictable and stable improvements without making any existing software slower (for the most part). They also realized that it's best not to couple big uarch shifts with big manufacturing shifts, and that power efficiency is of utmost importance. Hence why they transitioned to a tick-tock model. A brand new desktop uarch would basically be abandoning this. Even AMD probably feels this way, Bulldozer keeps more from K10 than people tend to realize.
Incidentally, we can still see big uarch shifts and trickle down in the mobile space. Silvermont looks like a fairly big change from Saltwell, A15 was a fairly big change from A8 and A9, etc. But they've just about caught up to the big technology apex P6 has as well, and we'll probably see tick-tock like refinement there from now on too. Intel has already said Silvermont is the start of tick-tock for mobile, and Cortex-A57, A53, and A12 appear to be incremental revisions to A15, A7, and A9 respectively.
With Netburst they didn't have that much big industry knowledge to tap into and instead moved into risky new experimental techniques. These would all perform well only if certain conditions were met. The long pipeline would perform well if the improved branch prediction was generally sufficient enough. The slow decode path would perform well if the trace cache had a sufficient hit rate. The tiny L1 dcache would perform well if the improved load to use latency offset the lower capacity. The double pumped ALUs would perform well if code avoided instructions not handled by them like shifts. So on and so forth. Of course it goes without saying that they also bet on eventually reaching a higher clock speed than they'd be able to. But it's all part of a common theme, the part had a ton of gambles.
Most of these things proved to not be true enough of the time and made for poor tradeoffs. Although you don't hear about it much the cost of missed R&D must have been immense.
Intel realized that at this point it makes more sense to stick with what works and incrementally refine it in safe ways that yield more predictable and stable improvements without making any existing software slower (for the most part). They also realized that it's best not to couple big uarch shifts with big manufacturing shifts, and that power efficiency is of utmost importance. Hence why they transitioned to a tick-tock model. A brand new desktop uarch would basically be abandoning this. Even AMD probably feels this way, Bulldozer keeps more from K10 than people tend to realize.
Incidentally, we can still see big uarch shifts and trickle down in the mobile space. Silvermont looks like a fairly big change from Saltwell, A15 was a fairly big change from A8 and A9, etc. But they've just about caught up to the big technology apex P6 has as well, and we'll probably see tick-tock like refinement there from now on too. Intel has already said Silvermont is the start of tick-tock for mobile, and Cortex-A57, A53, and A12 appear to be incremental revisions to A15, A7, and A9 respectively.