Why are the CMOS process sizes set the way they are?

[Chaotic42]

Right now most people are using a 65nm process for their circuits. Everyone keeps talking about going to 45nm next year. What is it that sets these sizes? What keeps Intel from going to say, 43nm, and AMD from going to 46nm?

Looking at Wikipedia, it looks like they've already got these things planned out to 16nm.

Just curious.

 

[imported_shader]

unfortunately IC fabrication is not my strong point. but i can probably clear something up. when they refer to a chip of the 65nm process, this refers to the 'average' feature size. so some components are smaller, some larger.

if your question is why do they use similar averages (45, 65, 90, etc.) that i cannot answer (probably due to limitations of silicon and elecrical interference between componts).

Some basic info on photolithography

 

[Special K]

Originally posted by: shader
unfortunately IC fabrication is not my strong point. but i can probably clear something up. when they refer to a chip of the 65nm process, this refers to the 'average' feature size. so some components are smaller, some larger.

if your question is why do they use similar averages (45, 65, 90, etc.) that i cannot answer (probably due to limitations of silicon and elecrical interference between componts).

Some basic info on photolithography

The process size refers to the drawn gate length. A 65nm process means the smallest gate length that can be drawn is 65nm. The actual fabricated gate will be smaller because the dopants will diffuse under the gate to some extent during the high-temperature processing steps.

I haven't yet encountered any reason to use a gate length greater than the minimum. If you need a slower/weaker transistor, you would generally alter the width of the device.

 

[Sohcan]

Originally posted by: shader
unfortunately IC fabrication is not my strong point. but i can probably clear something up. when they refer to a chip of the 65nm process, this refers to the 'average' feature size. so some components are smaller, some larger.

if your question is why do they use similar averages (45, 65, 90, etc.) that i cannot answer (probably due to limitations of silicon and elecrical interference between componts).

Some basic info on photolithography

I'm not an expert, but despite that Intel, AMD et al develop their processes independently, they do contract out to third-parties for tools and equipment. Having standard node sizes decreases the cost in using third-party equipment.

Originally posted by: Special K
The process size refers to the drawn gate length. A 65nm process means the smallest gate length that can be drawn is 65nm. The actual fabricated gate will be smaller because the dopants will diffuse under the gate to some extent during the high-temperature processing steps.

I haven't yet encountered any reason to use a gate length greater than the minimum. If you need a slower/weaker transistor, you would generally alter the width of the device.

Long channel fets are common in analog and tricky circuits due to variation in gate length being so large these days. If line edge roughness of the gate causes a 3-sigma variation of X% on a minimum gate length of Y um, then having a gate length of 4* Y um gives you variation of X/4%. They are nearly universal in analog circuits where fet matching is critical and layout matters.

Long channel fets are also sometimes used in tricky digital circuits such as feedback devices, which are often near minimum length and minimum width. Since minimum width devices suffer from variation as well due to the rounding of the gate at the edges, something that has 2x minimum width and length would provide the same performance with a lot less variation.

 

[darthsidious]

I think one of the reasons to use the same process numbers is because there are only a few suppliers for fabrication equipment (like Applied Materials, teradyne, etc.). Wit the cost of IC processing shooting up rapidly, the only way for IC fabrication being remotely affordable is for companies to place orders for similar pieces of equipment to lend economies of scale. That's also the reason the industry seems to move pretty much in lockstep (+/- a few months).

As for using greater than min length devices, there's quite a few reasons. Firstly, to make a device weaker than the min size device, you can't reduce the width any more (Limited by process). You have to increase the length. This is important in things like startup circuits (where you want some devices to be very weak). In addition, matching is strongly dependent on the area of the transistors. Min length transistors also have a ton of Vt variation with corners and bias points because of short channel effects like DIBL (Drain induced barrier lowering), and punchthrough. Finally (and most importantly for an analog designer like me), longer devices have higher output impedance for the same current levels, which allows you to build amplifiers with higher gain.

 

[BrownTown]

Also, all the process nodes are 1/2 the size of the previous one which i basically become the industry standard amount of shrinkage. Basically you could go from 90->80->70... but thats WAY to many new nodes which would costs you lots of extra money for only a small shrink. However its no better if you go 90->45->22 because that way there will be a very long gap between new nodes and you will get screwed in between. Shrinking by 1/2 is a good middle ground here. Also, in the world of gfx cards which get new refreshers every 6 months they do use half nodes to, so you have stuff like 110nm and 80nm etc.

EDIT: also, the nodes from different companies aren't all the same size either, they might both say 65nm, but one might be considerably more dense than the other.

 

[Navid]

Originally posted by: Special K
I haven't yet encountered any reason to use a gate length greater than the minimum.

That means you only design digital circuits.
In an analog block, you use larger than minimum gate lengths to improve device matching, increase output impedance, reduce noise ......

 

[f95toli]

Originally posted by: darthsidious
I think one of the reasons to use the same process numbers is because there are only a few suppliers for fabrication equipment (like Applied Materials, teradyne, etc.). Wit the cost of IC processing shooting up rapidly, the only way for IC fabrication being remotely affordable is for companies to place orders for similar pieces of equipment to lend economies of scale. That's also the reason the industry seems to move pretty much in lockstep (+/- a few months).

Exactly. There is something called the "International Technology Roadmap for Semiconductors" (ITRS) that ALL manufacturers use (more or less). The roadmap is a "plan" that representatives from all the sponsoring organizations and companies agree on and then try to follow. Essentially, it makes it possible for the companies that fabricate the tools to plan ahead. The ITRS is sort of the "bible" for the whole industry.
Hence, the reason why people talk about 65 nm, 45nm etc is because these values are the used in the ITRS.

You can find the latest roadmap at www.itrs.net

 

[Special K]

Originally posted by: Navid

Originally posted by: Special K
I haven't yet encountered any reason to use a gate length greater than the minimum.

That means you only design digital circuits.
In an analog block, you use larger than minimum gate lengths to improve device matching, increase output impedance, reduce noise ......

You are correct, I have only designed digital circuits so far

 

[Chaotic42]

Thanks everyone, this was really informative. :thumbsup: