Originally posted by: Fraggable
I was wondering, If Intel can make (single-core) 3.8GHz Prescott processors using a 90nm process, why do AMD processors top out at 2.8GHz (FX-57) if they're 90nm too? Everyone knows that Prescotts run way hotter than AMD 64's have ever thought about running so heat shouldn't be a problem. I also know that an FX57 will outrun a 3.8GHz Prescott in most applications but still, why can't they make them any faster?
Maybe it's a stupid question and you'd have to know more about their architecture to understand it, but it doesn't make sense to me.
1. AMD has more execution units than Intel, so they should be producing more heat per mhz.
2. AMD has a shorter pipeline, and thus can't clock as high. AMD's is like 12 to 14 stages, while Intel's is 31 stages. Intel's chips were designed to get up to 5ghz, but heat barriers stopped them, AMD chips were never designed to clock that high. (IBM's G5s were designed to clock to 3.2ghz I believe, but heat barriers stopped them as well) I don't know what frequency AMD was aiming for when they designed their chips, but I'd imagine they're pretty close to it.
At first, the higher clocks bested the Athlons, but as AMD got their speeds a little higher, Intel's pipeline penalty began to show more and more. Amd's FPU also got better.
At 2nd actually, the early P4s were rushed out and took a while before they could even beat the considerably lower clocked P3s in performance, and even longer before they could match the not much lower clocked initially and higher performance per mhz athlons. (P4s launched at 1.8ghz versus a 1.4ghz athlon, the athlon typically had a 25% performance advantage over the P4 and was cheaper)
actually it's more intel that lengthened their pipeline going from p3 to p4 in order to be able to reach higher clocks while AMD kept their short pipeline
Actually, it's more like AMD increased the pipeline to clock higher and added additional execution units to increase performance per mhz, then Intel did so to the absolute extreme and added additional hardware to keep performance viable.
The DEC Alpha and the IBM Power4/G5 did both, but I think their pipelines are closer in size to AMD's than Intel's.
BTW, as for the P4...performance does scale fairly linearly in clock speed with some things, in fact it scales better than AMD's additional execution units did. Serial execution > parallel execution. Thus Conroe, since Intel's always been at home on media benchmarks, but an Athlon will rock a Pentium M at media benchmarks due to being able to take advantage of the additional execution units(though core duo should help there a lot). Really, the P4 design is superior to the Athlon's, at least until they hit a heat and clock speed barrier. Any parallel algorithm can be made serial, but not any serial algorithm can be made parallel. About the only thing the P4 lost out on was branchy code (which is the prime area current x86 cpus beat out other cpu architectures, and the prime area AMD's integrated memory controller benefits), which could be overcome as long as the frequency was kept high enough.
u forgot to mention, how the top will use 1.37V while the second one will most probably need double if not tripple the voltage hence making all the electricity goto waste
Umm, the P4s use about the same voltage, if not lower, just the amp draw is considerably higher.
I see a lot of misinformed people who actually believe Sempron64 3000+ (1.8Ghz) can actually top a 1.5Ghz Celeron-M/1MB. Guess what, the Sempron is 10 stage and the Dothan based Celeron-M is 14. Shocker.
Off hand, I'd guess they're approximately equal, with one taking some benchmarks and the other taking the rest. (Btw, I always thought the Celeron and Pentium Ms were estimated at 10-14 stages, was it ever revealed how much? And pretty sure the sempron is 12 or 14.....also are we talking integer or floating point pipeline stages? in the ppro to p3 architecture the integer pipeline was heavily pipelined, but the floating point wasn't, I don't think the p3 even had pipelined floating point, while the athlon's floating point usually has about 2 pipeline stages beyond integer)
BTW, with all the power leakage going on in modern cpus, would it be possible to make a cpu that actually takes advantage of the power leakage to power other parts of the chip? Or is the power leakage purely heat energy and not electrical?
FYI, if intel stuck with a P3 design and just did die shrinks, it would suck horribly. Even if they took the P3 and deepened all its buffers to say, as deep as merom. It would still be a crippled chip utilizing a mere fraction of its available floorspace, with crappy throughput because of its short, low frequency pipeline.
The ~10 million logic transistors P3 core was getting raped by the approximately ~30 million logic transistors Athlon core at the time it was retired. (and as long as P4 maintains twice the clock speed of the other cores, it should beat them in every situation)
Kind of interesting that AMD has almost always had faster cores than Intel, but Intel in the past often had better performance due to having a better handle on fabrication. (only with the athlon core versus an outdated ppro and a rushed p4 did amd temporarily have the better core, then again with the integrated memory controller versus the p4 hitting unexpected limitations)
Take the Cell for example. It reaches 200 GFlop, where a P4 with 3,2 Ghz makes 25,6 GFlops. That's just for Matrix Multiplication, in Linpack it reaches 156 Gflops, where the P4 is at 25,6 too.
And then there's developers who claim it has less performance than a Pentium 3 at branchy code, so it's not like there weren't trade offs with the Cell design. A more powerful general purpose core would make the Cell a dream design though, and with the high programability of its additional cores I wonder if maybe it could model the OOE hardware of a Pentium or Athlon.
The Cell is a 8way SPE/PPE. The assembler for is so massively difficult to program its not even funny. Algorithms are still pretty much under development. To fully utilize Cell, it'll take literally a GENERATION's worth of doctoral thesis's and research.
Maybe so, but I think it's multicore model sounds genuinely superior to the current pc way of just adding more of the same core, and especially to the x360 cpu, which I can see no benefit too other than microsoft owning the IP.
I think of Cell as the logical extension of the current programming model, we already have stages (hard drive, memory, L3 cache, L2 cache, L1 cache, registers, pipelining), so why not go Primary core -> Secondary Core -> Tetiary Core, and so on? All the cell cores have high speed interconnects between them, so it sounds logical to do something assembly line style.
Oh, and I believe on AMD's roadmap they list the quad core K8 as having architectural revisions to increase single threaded performance.
BTW, next cpu philosophy is likely to be cell like designs, dedicatedish hardware for different tasks backed by a single powerful Athlon or Pentium M like core for code management.
Oh no, you are a little dis-informed. They told Apple, they will have 3 Ghz G5s by 2004, but they have it now. But they have not simply 3 Ghz, they have DualCore 3 Ghz, so a 3 Ghz Quad would be possible at the moment, the only question is: Does Apple still want this? It would be hard to be topped out by a Conroe based Mac this year.
The reason why IBM did only reach 2.5 Ghz in 2004 and not 3 Ghz was unexpected difficulties in the 90 nm process, which ALL MAJOR CPU-MANUFACTORS HAD.
Intel said to reach 4-5 Ghz with the 90 nm process. Do you notice something?
IBM said they solved the problems with higher clock frequencies, and will bring a 5,6 Ghz Power6 CPU.
IBM says a lot of things about clock speed, they've never been able to tackle Intel though. As of right now, despite a longer pipeline and lower performance per mhz (often significantly), the G5 is always + or - 100mhz of whatever the fastest Athlon is. Currently, isn't the G5 at 2.7ghz, with a 2.9ghz coming soon? Considering AMD and IBM use the same fabrication tech, that's not very impressive. Or can I now buy a G5 at 3ghz? Anyway, it doesn't really matter, the horrible memory controller (why does something using high speed DDR or DDR2 have memory latency on par with an ancient VIA chip using PC2100?) ruins most of the potential performance of the chip. (which seems way too focused on SIMD performance anyhow, as Opterons and P4s can usually match or beat it, sometimes signficantly, in most everything else, and the Opterons and SSE3 P4s can even come close to its SIMD performance)