Originally posted by: Cerb
In the chip, there is a pipeline to get things done...all the stuff it needs to do go through this pipeline (it is called a pieline for a reason).
The pipeline has stages, and each one does a small amount of work.
IIRC, each stage has a single clock cycle to do its work, then it pushes it to the next stage.
So, the P4 has a longer pipeline. So that means each one can do less work, so to keep up with the power of chips with smaller pipelines (like their own PIIIs), it must reach a significantly higher clock speed, since they are doing less each cycle.
The P4's higher clock speed and wider memory bus lets it shove around more information, hence its dominance in video benchmarks; though the price is that it loses processing power to do that. There are more disadvantages to longer pipelines than just less power per clock. IIRC, if the chip has to wait for memory to give it something and the pipeline needs to be filled again, since it does less, it takes longer. This is part of why the prediction part of the chip was such a big deal going to the northwoods (something about having such high clockspeeds and not being able to get signals across the CPU in a single cycle).
The current Athlons are more on the side of raw calculation, and likely that will continue with the Hammer, since, for one thing, it gives it a niche.
here's a good link I found:
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