Why Do Pentium 4 processors overclock better than Athlon XPs?

[arcenite]

Plain and simple. P4 core is built to run at fast speeds, and that's where their power comes from. XP core is built to run slower but be able to do more per clock.

Bill

 

[Nemesis77]

Here are facts regarding thermal properties of P4 and XP. Interesting tidbits:

Pentium 4 3.06 GHz
typical thermal power: 81 W
Maximum thermal power: +/- 105 W

Athlon XP 3000+ (Barton)
Typical thermal power: 58.4 W
Maximum thermal power: 74.3 W

 

[Ilmater]

Originally posted by: Cerb
In the chip, there is a pipeline to get things done...all the stuff it needs to do go through this pipeline (it is called a pieline for a reason).
The pipeline has stages, and each one does a small amount of work.
IIRC, each stage has a single clock cycle to do its work, then it pushes it to the next stage.
So, the P4 has a longer pipeline. So that means each one can do less work, so to keep up with the power of chips with smaller pipelines (like their own PIIIs), it must reach a significantly higher clock speed, since they are doing less each cycle.
The P4's higher clock speed and wider memory bus lets it shove around more information, hence its dominance in video benchmarks; though the price is that it loses processing power to do that. There are more disadvantages to longer pipelines than just less power per clock. IIRC, if the chip has to wait for memory to give it something and the pipeline needs to be filled again, since it does less, it takes longer. This is part of why the prediction part of the chip was such a big deal going to the northwoods (something about having such high clockspeeds and not being able to get signals across the CPU in a single cycle).
The current Athlons are more on the side of raw calculation, and likely that will continue with the Hammer, since, for one thing, it gives it a niche.

here's a good link I found: Google is God's search engine.

You're kind of right. The problem is, if there are any errors in the strings, the whole pipeline has to be flushed and rerun. Branch prediction is a big problem for the P4 (versus the AXP) because it has to refil all 20 stages of its pipeline if it has any errors or mispredictions in the data. I'm very curious as to why having moer pipelines means you can increase the clocks, but somehow it does.

IIRC, the AXP has 8 stages, right?

As for why the P4s overclock better, please remember that if I buy a 1700+ and clock it to 2.25GHz, I'm getting the equivalent of an 1100MHz increase in clock speed on a P4 (1700+ -> 2800+). So, while many are getting 1.6As that OC to 2.4s, that still isn't as good as what the 1700+s are getting.

 

[paralazarguer]

no, the 80 watts is the amount of heat being dissappated, they both run just as hot.

Yes, you're right but you don't get it. They both dissipate the same wattage (in this example) but one has a larger surface area therefore does it faster. It runs cooler.

 

[superbooga]

More pipeline stages mean each each stage does less work. Each stage must complete it's work within one clock cycle. If there is less work to be done, then the clock cycle can be increased while still maintaining a safety margin.

 

[Athlon4all]

The pipeline is a factor in itself, but there's 2 other factors:

1. The age of the K7 Architechure vs the age of the P4 (think back to the P3!). The P4 is little more than 2 years old, the K7 is gonna be 4 years by the time the K8 hits.
2. The maturity of Intel's .13um process vs. the maturity of AMD's .13um process (even after the T-Bred-B and Barton).

 

[imgod2u]

The number of pipeline stages (for integer and FP) are a part of the architecture. I don't see what the age of an architecture neccessarily has to do with the scalability. The P3 design is certainly older than the PPC G4+ design yet it is more scalable.
As for number 2. I'm not sure about the intricaces of lithography (perhaps Wingnutz can fill us in) but just exactly how superior do you claim Intel's processing technology is? Last that I recall, AMD used a far more elaborate (and expensive) processing method requiring more layers of metal to make up the interconnects in its processors to guarantee signal stability at high clockrates.

 

[Wingznut]

I guess you can look at it a couple of ways, imgod2u... I wouldn't give credit to AMD because they are using 9 metal layers in their process. Adding the extra layers obviously adds to the cost and most likely lowers the yields (add in more manufacturing steps and you get more chances for error.) Adding cost to the process is NOBODY'S goal.

And actually, I would give props to Intel's design for being able to stay at six layers and still consistantly deliver the high end product. Delivering to market is definitely an area where AMD has faltered. And it doesn't really matter what your design is, or how many times you've shown a proof of concept, if it's not on the streets.

Now, adding the extra metal layers allowed AMD to scale this (relatively) old process even further. I'm sure the K7 has lasted longer than anyone predicted when it began. So, had the K7 been a better design, maybe they wouldn't need to add layers. Of course, had they been able to deliver Hammer by now, this would be a moot point.

Yep, I've pretty much flipped, flopped, and then flip-flopped again. The gist is that you can't really say one is better than the other, with maybe the exception of being able to deliver.

I just think it's simply amazing that a piece of glass (silicon wafer) can go through hundreds of manufacturing steps, with only angstroms of room for error, and in the end I can sit here and type replies on a msg board... And maybe play some Unreal 2.

I do this stuff for a living, and still... Every single day I look around the fab in awe.