do you even read what I write? wild speculation? square wheels? It really isnt that hard to get. We both know that DRAM is made of a bunch of cells containing a transistor and a capacior which are addressed in a maxtrix like implimintation wth a row and colums adress. The cells are activated by bug ass decoders which take the adress bits and activate the correct adresses. Now these decoders have n inputs and 2^n outputs which can be activated, but there is nothing saying that all 2^n lines have to actually be used. If the OS knows that there are only 700MBs of RAM then it will only send adresses which exist in the RAM and wont try to adress the non existant 700-1024MB adresses. I can see no reason why it would not work on CURRENT imlimintations.