Well, at 10nm the most important thing they could do are:
- Put fins (and interconnect wires and gates) even closer together (for about 2x more transistors/mm²)
- Make gate even shorter
- Put III-V and Ge in the channel for higher performance (mobility) and (potentially vastly improved?) lower power
- Improve the fin with a quantum well, which will result in 3 sides being controlled by gate + the 4th side isolated
We'll just have to see what they have done. It's been a long time since 14nm+10nm density plans were disclosed (3 years now) and 2 years since 14nm transistor briefing, and it will still be another year until the new transistor gets released .