Why node designations don't matter

[IntelUser2000]

Here's my reply for the guys at Vega thread: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/vega-navi-rumors-updated.2486940/

No, it isn't. 28 to 20 is a "half node". Just to like 20 to 14 is half a node.

Correct. Stuka87 gets it.

I think people are getting mixed up because they remember a full node is half size/double density, and it is. But that is based on area and node names are based on linear measurement.

No.

I should have added. "In Theory".

Remember Intel complaining that it's competitors node names were bullshit? This is what it is all about.

Their assertion is right. However, I believe their numbers are in practice, shady as well.

That would suggest Intel is coming no where close the theoretical density of their process which is probably based on the size of an SRAM cell.

I would assume so. Or its a lot more complex.

Why are Foundrys' node numbers a marketing number and does not necessarily reflect reality?

Because post-28nm nodes use full node names for half nodes. Pre-28nm, going from 110nm to 90nm was a half node, as it should be. 130nm to 90nm would be a full node. However, post-28nm it changes. Why? Because scaling started to become really hard. And transistor performance benefits started to diminish. Because manufacturers wanted to perpetuate the notion that "everything is fine" they named 20nm and 14/16nm when in reality it should have been a half node.

20nm = 28nm with double the density(conversely half the size)
14nm = 20nm density but with FinFET transistors for performance

So most manufacturers "skipped" 20nm and went from 28nm to "16/14nm", because they NEEDED that to get full node benefits. Traditionally a shrink brought both the density gain and performance gains. With post-28nm they needed FinFET to get the full node performance gain. Hence, 28nm to 16/14nm is a single, full node reduction, not a double full node reduction. It's a double half node reduction.

Is Intel completely correct in saying they have a massive density lead?

This is questionable.

Ivy Bridge 4C GT2 1.958mm2 per 1MB L3, Total = 160mm2 1.4 billion transistors(8.75 mil tr/mm2)
*Broadwell 2C GT2 1.09mm2 per 1MB L3, Total = 82mm2 1.3 billion transistors(15.6 mil tr/mm2)
*Knights Landing 0.7mm2 per 512KB L2 Die, Total = 650mm2 ~8 billion transistors(12.3 mil tr/mm2)
*Skylake 1.2mm2 per 1MB L3

Since I've calculated the Total numbers above, let's calculate the million transistors per mm2(mil tr/mm2) for the caches. It uses 6T setup for the caches so it takes 6 transistors per bit. 6 transistors x 8 bit per byte x byte to MB conversion(1024x1024) = 50.3 million transistors

Ivy Bridge L3 cache density = 25.69 mil tr/mm2
Broadwell L3 cache density = 46.15 mil tr/mm2
Knights Landing L2 cache density = 35.9 mil tr/mm2
Skylake L3 cache density = 41.9 mil tr/mm2

Caveats for the chips with * next to their names
-Chips Post Ivy Bridge Intel started the practice of hiding transistor and die size metrics. We get the numbers until Haswell. After that, its hard to find
-Knights Landing numbers are approximate, though it shouldn't change more than 20%
-Broadwell has blurry shots. 10% margin of error
-Skylake has a weird cache configuration. Should be more accurate than Broadwell though.

For comparison, Ryzen has an L3 cache density of 1.0mm2 per 1MB L3 cache. ~50 mil tr/mm2. This number is quite accurate.

Ryzen has 3x the transistors of Intel chips. Total transistor numbers became irrevalent.

Courtesy of Paratus:
Ryzen is 4.8B with 195mm2 for 24.6MTr/mm2

4C GT2 Haswell had a transistor count of 1.4 billion. It's unlikely we're much higher with Skylake.

SRAM(caches) are by far the majority of the consumer of transistors.

Ryzen's caches

8x 64KB I-cache
8x 32KB D-cache
8x 512KB cache for L2
2x 8MB cache for L3
Total: 20.75MB of cache

Haswell 4C GT2:
4x 32KB I-cache
4x 32KB D-cache
4x 256KB L2 cache
1x 8MB L3 cache
Total: 9.25MB of cache

But wait, you might say, Ryzen has TWICE the amount of cores! That doesn't matter. Because cores take a small amount of transistors. Let's compare it to Broadwell-E shall we?

Broadwell-E 10 core, 3.4 billion transistors, 246mm2 die = 13.8 mil tr/mm2. Ryzen still has 40% more transistors.

10x 32KB I-cache
10x 32KB D-cache
10x 256KB L2 cache
1x 25MB L3 cache
Total: 28.125MB of cache

28.125(BDW-E) - 20.75(Ryzen 8C) = 7.375MB of cache! Or 7.375 x 50.3 mil tr = 371 million more transistors used up in caches for Broadwell-E. Yet, Ryzen has 1.4 billion more.

Transistor counts at the whole don't matter. What is Ryzen using the transistors for? Since the die size is pretty compact, we don't really care. Unlike Vega, which has a huge amount of transistors ending up in a very large die.

Conclusion:

Intel claims in their presentations that competing 14/16nm solutions have a transistor density of 25-30 mil tr/mm2. Ryzen 8C has an L3 cache density of 50 mil tr/mm2, which is far higher than that.

I call Intel's tactics as "shady" as other Foundries are "shady". Because in practice there's little difference. You can not equalize it like you do with benchmarks to do a "fair" comparison.

-Intel numbers don't matter because they basically only make their chips.
-Transistor density is heavily influenced by implementation. I suspect the reason Ryzen is quite dense and Intel chips not is because the latter is optimized for performance. You need more transistors and larger transistors to get greater drive current and get higher clocks, or lower instruction latency(for per thread performance).
-Density metrics are not as important as before because the transistors themselves may not be as high performance. Yes, Intel's 10nm may be dense, but who cares when they themselves claim 10nm is lower performing than 14nm++?

It seems Intel started using weird density metrics and focus on density when they started offering Foundry services! How about Intel, focus on things that matter because right now no one uses your Foundry. YOUR chips are used, which is what the process should be made for.

Node numbers are basically marketing numbers. Only products speak the truth. Post 32/28nm, the numbers mean little. It just means its better than the previous generation. How much better? You'll know it when you get the product.

 

[PeterScott]

Node names actually have a standards body that defines, them

Here's my reply for the guys at Vega thread: http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=threads/vega-navi-rumors-updated.2486940/

Correct. Stuka87 gets it.

No he doesn't, and by extension then, neither do you when you say he does. If he actually got it he would have said it was named like a full node but in reality the shrink wasn't that large, or something to that effect. He didn't, because he just didn't get it. He apparently thought a .7x shrink represented a half node, which is incorrect.

28nm to 20nm is by definition an official full node. That represents a .7 shrink, which is what a full node is.

Check anywhere for the definition of full node and half node.
https://en.wikichip.org/wiki/technology_node
"Half node, much like the process term also dates to the 1990s when incremental shrinkage was readily achievable. A full technology node was expected to have a linear scaling shrink of 0.7x (e.g. 130 nmafter a full shrink yields 90 nm). Similarly, the associated half node was then expected to have a 0.9x linear shrink."

Full Nodes are 0.7x linear shrink Half nodes are .9X linear shrink.

This is the correct nomenclature.

By the correct nomenclature 28 x .7 = 20 = Full Node.

It's clear what an official node name means. .7x linear shrink.
----------------------------------------------------------------------------------------------------------------------------------
Now, onto The Mess:

What is actually going behind the scenes is murky. Nearly impenetrable Murk. As you have pointed out densities change wildly on the same process, seemingly small structures seem to gain huge transistor counts. It makes it pretty much impossible to get any kind of sensible read on something we can compare for transistor density.

So yes Node names no longer have a direct mathematical connection to their names, marketing is too involved.

Now what they call a full node is largely when a Foundry packages up enough improvement, some performance, some power, some density, to be be considered a nice jump, they tend to label it as a full node.

Like the recent TSMC 16nm to 12nm FFN. This is almost a full nodes linear shrink (.75 instead of .70), yet there seems to be almost no transistor gain comparing similar products from the same manufacturer (GV100 vs GP100). It seems mainly to be power reduction enhancement.

It's not that Node designations don't matter. It's that the designations can't simply be looked up as 1:1 shrinkage representation as they did a long time ago. Each Node designation still means something.

GloFo 14nm is still better than GloFo 28nm, GloFo 7nm will be better than GloFo 14nm. Outsider just can't apply a simply mathematical relationship to determine how much better they are. Insider likely get a think document explaining all the changes in detail.

 

[eek2121]

Node names actually have a standards body that defines, them


No he doesn't, and by extension then, neither do you when you say he does. If he actually got it he would have said it was named like a full node but in reality the shrink wasn't that large, or something to that effect. He didn't, because he just didn't get it. He apparently thought a .7x shrink represented a half node, which is incorrect.

28nm to 20nm is by definition an official full node. That represents a .7 shrink, which is what a full node is.

Check anywhere for the definition of full node and half node.
https://en.wikichip.org/wiki/technology_node
"Half node, much like the process term also dates to the 1990s when incremental shrinkage was readily achievable. A full technology node was expected to have a linear scaling shrink of 0.7x (e.g. 130 nmafter a full shrink yields 90 nm). Similarly, the associated half node was then expected to have a 0.9x linear shrink."

Full Nodes are 0.7x linear shrink Half nodes are .9X linear shrink.

This is the correct nomenclature.

By the correct nomenclature 28 x .7 = 20 = Full Node.

It's clear what an official node name means. .7x linear shrink.
----------------------------------------------------------------------------------------------------------------------------------
Now, onto The Mess:

What is actually going behind the scenes is murky. Nearly impenetrable Murk. As you have pointed out densities change wildly on the same process, seemingly small structures seem to gain huge transistor counts. It makes it pretty much impossible to get any kind of sensible read on something we can compare for transistor density.

So yes Node names no longer have a direct mathematical connection to their names, marketing is too involved.

Now what they call a full node is largely when a Foundry packages up enough improvement, some performance, some power, some density, to be be considered a nice jump, they tend to label it as a full node.

Like the recent TSMC 16nm to 12nm FFN. This is almost a full nodes linear shrink (.75 instead of .70), yet there seems to be almost no transistor gain comparing similar products from the same manufacturer (GV100 vs GP100). It seems mainly to be power reduction enhancement.

It's not that Node designations don't matter. It's that the designations can't simply be looked up as 1:1 shrinkage representation as they did a long time ago. Each Node designation still means something.

GloFo 14nm is still better than GloFo 28nm, GloFo 7nm will be better than GloFo 14nm. Outsider just can't apply a simply mathematical relationship to determine how much better they are. Insider likely get a think document explaining all the changes in detail.

I find it hilarious that this topic keeps coming up. In a third world country? Maybe. However, this subject is brought up in a US demographic. A demographic that is so lawsuit happy that you can be sued for even giving someone a funny look under the right circumstances...despite the constitution. Why does that matter? As I have tried to hint at in the past, if a company claims to have an Xnm process, they better hope to god they can prove it. If Intel has a 'real' 14nm process and AMD does not, Intel could successfully sue AMD in court here in the US. However, it gets deeper. If Intel or AMD claim that they have 14nm process and the math doesn't check out, we the consumers get to sue instead. So now you are left wondering..."so why hasn't it happened?!?". The answer is, it's likely so close that neither corporations or consumers could successfully prove their case in court...and keep in mind our legal system was in favor of a lady who spilled 'hot' coffee in her lap, in in favor of OJ simpson, etc. I'll make a bold claim and tell you that Intel, Glofo, Samsung, etc. are all within margin of error with each other. Any statements contrary are likely false rumors intentionally spread by competitors. Do you have proof otherwise? Contact a good lawyer, you'll likely win a good chunk of change if you do.

 

[IntelUser2000]

No he doesn't, and by extension then, neither do you when you say he does. If he actually got it he would have said it was named like a full node but in reality the shrink wasn't that large, or something to that effect. He didn't, because he just didn't get it. He apparently thought a .7x shrink represented a half node, which is incorrect.

28nm to 20nm is by definition an official full node. That represents a .7 shrink, which is what a full node is.

Check anywhere for the definition of full node and half node.
https://en.wikichip.org/wiki/technology_node
"Half node, much like the process term also dates to the 1990s when incremental shrinkage was readily achievable. A full technology node was expected to have a linear scaling shrink of 0.7x (e.g. 130 nmafter a full shrink yields 90 nm). Similarly, the associated half node was then expected to have a 0.9x linear shrink."

Full Nodes are 0.7x linear shrink Half nodes are .9X linear shrink.

This is the correct nomenclature.

By the correct nomenclature 28 x .7 = 20 = Full Node.

It's clear what an official node name means. .7x linear shrink.

You are still hung up on the theoretical.

20nm is half the size(or twice the density for those that prefer it this way) of 28nm. 14nm is ~ 20nm in density.

Therefore, by results speaking for itself, 14nm = ONE full node from 28nm

They can claim what they want, but what they say it is, and what it actually is does not match. The manufacturers continue to propagate the old belief that new processes are just like the old ones because they don't want to admit that traditional Moore's Law scaling is dying.

If in the future they claim a 2nm process but is half the size of a 10nm-named process would you still hand around the Wiki link about what a full node is? You'd be doing the misleading just like the manufacturer. You should be saying while the old designations meant such and such the new ones are different.

 

[IntelUser2000]

A look at one particular example.

The whole bit about whether node designations are "real" happened with 22nm. That is to specifically say when Intel brought their 22nm TriGate process in 2012.

When they actually disassembled the chip and looked at the transistors individually, they found out the Gate Length was 25nm. People went up in arms!

Really though, it did not matter one bit. Because the products spoke for themselves. The chips offered roughly 2x the transistor density at the same area. So, all fine and dandy.

Why did then people complain about Gate Length being bigger than node numbers? Because up until then, the general smallest feature set determined the node numbers. Not always, there's a caveat to everything, including this but that was roughly the case. And Gate Length happened to be the smallest part of the transistor. And now people couldn't tell what "22" really meant. But I say, as long as the results are true...

So why did they have to stop scaling Gate Length as much as the rest of the transistor?

Simply, because humans that are measured in meters(or feet) with fingers and hands measured in centimeters(or inches) are trying to work with things that are small as the cells that comprise them. And the tools that should be smaller isn't working out as it should be(as is the case with EUV).

Basically, the smallest feature set size was the limiter and if you made that part proportionally smaller, it'd make it unreasonably hard, which would mean decreased yields, and increased costs. Traditional scaling dictates smaller gate length meant higher performing transistors. If you can't scale down, the performance sucks, even if you can get more transistors. So with 22nm Intel went by increasing the number of gates.

2 generations before that, Intel brought Hi-K dielectrics to their transistors. The dielectric thickness of 65nm chips were already too thin to be manufactured, so they couldn't make it smaller on 45nm. Hence they brought a different "Hi-K" material so the dielectric could be much thicker, yet having performance improvement of a thinner gate.

So in the end, it did not matter if 22nm didn't have 22nm gates. Because you could still fit twice the amount of circuits as with 32nm.

 

[PeterScott]

You are still hung up on the theoretical.

20nm is half the size(or twice the density for those that prefer it this way) of 28nm. 14nm is ~ 20nm in density.

Therefore, by results speaking for itself, 14nm = ONE full node from 28nm

They can claim what they want, but what they say it is, and what it actually is does not match. The manufacturers continue to propagate the old belief that new processes are just like the old ones because they don't want to admit that traditional Moore's Law scaling is dying.

If in the future they claim a 2nm process but is half the size of a 10nm-named process would you still hand around the Wiki link about what a full node is? You'd be doing the misleading just like the manufacturer. You should be saying while the old designations meant such and such the new ones are different.

Node only has a theoretical meaning today. But that is the same as it ever was. A .7 linear shrink of the numerical value in the NAME.

It is unlikely that the real linear values have matched this in over a decade, heck gate length divergences began in late 1990s.

Practical and theoretical often diverge.

Yeah, it sucks that the divergence has gone increasingly wonky.

But lets not get off into the weeds making up new definitions to suit one special case.

 

[JoeRambo]

Node only has a theoretical meaning today. But that is the same as it ever was. A .7 linear shrink of the numerical value in the NAME.
.

I'd say the nowadays naming is completely arbitrary and fully driven by marketing departments, "0.7 rule" does not really apply in any way. For example 16nm -> 12nm TSMC is 0.75 "linear shrink of the numerical value", but i guess even MBA's from marketing don't call it "full node". Performance of actual devices in density, clock, power and actual performance is what matters the most.

And sadly that is where all this great technical talk hides the total and utter failure of AMD to extract anything from doubled density and FinFET transistors. It does not matter exactly how many X.Y node shrinks there were between 28 and 14/16nm, but when compared to what Nvidia and Apple, QC did going from 28nm, AMD's failure is shining HARD.

 

[AtenRa]

Glofo 28nm bulk to 20nm bulk is not half note. Also GloFos 20nm Bulk to 14nm FF LPE/LPP is not half node.

Glofos 28nm Bulk was supposed to be half node of 32nm SOI.

TSMC 55nm was half node of the TSMC 65nm.

 

[PeterScott]

I'd say the nowadays naming is completely arbitrary and fully driven by marketing departments, "0.7 rule" does not really apply in any way. For example 16nm -> 12nm TSMC is 0.75 "linear shrink of the numerical value", but i guess even MBA's from marketing don't call it "full node". Performance of actual devices in density, clock, power and actual performance is what matters the most.

Even worse 12nm FFN from TSMC is nowhere near a .75 linear shrink on the actual silicon. It's not even be .9 shrink of a half node.

http://www.anandtech.com/show/11367...v100-gpu-and-tesla-v100-accelerator-announced

GV100: 25.9 Mtrans/mm2
GP100: 25.1 Mtrans/mm2

It's essentially no shrink at all moving for 16nm-12nm. By transistor density this isn't a full node or half node shrink. It should have been called 16nm+. Assuming 16nm had any real meaning.

Node names are completely abused today. It would almost be better if they started naming them by generation. Or generations since the year 2000 since everything went off the rails.

Anyone going to use an actual process will no doubt get precise linear/density/power/leakage/etc measures, so what they call it is irrelevant to them.