Will AMD Phenom beat CD2???

[coldpower27]

Originally posted by: aigomorla
WAIT, penryn will come out this november in the form of QX6950.

So whats all this talka bout it coming out 10 months from now?

IF you can afford it, you can pick one up in 2 months. I know i will be picking one up and having massive amounts of fun with it.


And i still think AMD is a lost cause.

Originally posted by: Blacklash
Overclocking does change the picture quite a bit. Look at what folks are already doing with Q6600 G-0s on average:

http://www.xtremesystems.org/f...?p=2410961&postcount=2

Now if the 45nm chips are 200MHz better than this we could soon see 4.0GHz with Quad core on air with a decent after market cooler. I know folks are already booting up to 4.0GHz on air and I am talking Quad core and Prime stable.

SHOW ME 1 computer whose booting up priming @ 4.0ghz Stable on air on ANY Quad B3 G0, ES even.

My ES is on a UBER water setup, and thats how i kept her stable. The board is on water, cpu on water, and im not talking about entry lvl, or even mid level water. Im talking about full blown PA120.3 with dual DDC-2's on a Copper top ApogeeGTX bowed.

Infact, even for water 4.0ghz prime stable is VERY VERY difficult, and will definitely shortn the life of your CPU + Board.

So what are u smoking? Care to share?

The people of this forum were discussing that it was coming out 10/12 months from tapeout which happened in November of 2006, so Penryn derivatives should arrive sometime in Q4 2007, so before the end of the year. We of course already know that Harpertown is coming in on Rememberence Day's, though we have no idea currently for Yorkfield XE.

 

[Viditor]

Originally posted by: Idontcare

Originally posted by: Viditor

Originally posted by: jones377
Penryn taped out in late November last year. First samples arrived in early January.

Tapeout
First samples

Since it's expected to be released towards the end of the year that makes it pretty much 12 months from tape-out to shipping.

You got that backwards...first samples in preperation for tape-out were in November, tape-out was in Dec/January.
Daily Tech

"Sources inside Intel have confirmed the company recently received the taped-out 45nm Penryn processor"
"Penryn, the 45nm optical-shrink of the Core architecture, was prepped for tape-out in late November, and returned to the Intel development team just a few weeks ago"

Penryn is to launch November 11th. Shipping should begin the month before (unless they are doing a paper launch).
DailyTech

So 9 months, maybe 10...

For some generally accepted definitions and example uses of the term "tape-out" see:

Tape-out is usually a cause for celebration by everyone who worked on the project, followed by eager anticipation of an actual product returning from the manufacturing facility.
http://en.wikipedia.org/wiki/Tape-out

Tape-out refers to the release of the layout design package to the manufacturing fab for the creation of photolithographic masks. Practically it means that the chip developer is confident in the released design.
http://www.xbitlabs.com/news/c...ay/20061019222838.html

I am quite familiar with tape-outs and a large portion of Fab techniques...I am also familiar with the first samples that are created prior to tape-out.
The first tape-out is the production mask used for an entire wafer to create rev A0...
The samples that you thought of as the first tape-out are when they use various masks on a single wafer and test them to find the best production mask design to replicate on to the entire wafer for the first tape-out.

Viditor, you have no clue what tape-out means, it's obvious

You shouldn't throw stones in glass houses...

 

[IntelUser2000]

AMD's Phemon has better scaling per clock than Core 2 Duo at 65nm. But no one knows how it will do against the 45nm chip.

The P4's scaled pretty well. It doesn't mean it performed well. When a chip scales unusually well it means the platform is too good for the CPU, or the CPU is too crappy for the platform. You mention PC8500 and HTT bus making a difference. Well, numerous reviews have shown that faster HTT bus absolutely nothing for performance, staying well within margin of errors. PC8500 isn't too much useful, ever since AMD put IMC, changes in memory performance was also very small. Both AT and Techreport results point out Phenom being around 10% per clock disadvantage to Conroe/Kentsfield.

Scaling page: http://www.anandtech.com/cpuch...howdoc.aspx?i=3092&p=6

"Just as before, the benchmarks run are our standard CPU tests with the exception of the gaming benchmarks which are run at 1024 x 768 to ensure that they are CPU bound":

Yay. You don't think Core 2 would scale that well with Geforce 8800GTX and 1024x768 resolution?? You can't even compare to AT's first official Core 2 Duo results as they used 1600x1200 to simulate "real" world benchmarking.

Translating it into scaling...

Barcelona(2.5/2.0GHz)

WME: 93.6%
iTunes: 58%
3dsmax R9 SpecCapc: 84.8%
Oblivion: 66.4%
Half Life 2: Episode One: 65.6%

Core 2 Duo(E6700/E6600, from first Anandtech Core 2 Duo review)
WME: 98.9%
iTunes: 63.7%
3dsmax R7(Composite score): 103.5%
Oblivion: 74.7%(Burma), 55.6%(Dungeon)
Half Life 2: Episode One: 24.1%

As we can see they scale around the similar rate, and we can even say Core 2 Duo scales better per clock. 3dmax scores use different benchmark, but scaling rates shouldn't change greatly between benchmarks, and Core 2 Duo offers much greater scaling than Barcelona does. Oblivion scores aren't directly comparable as Barcelona tests show limited details, but it lies between Burma and Dungeon scores for Core 2 Duo. Half Life 2 had poor scaling of performance for Core 2 Duo, but its eskewed by the fact that its becoming GPU-bound at that performance range, while Barcelona is nowhere limited by the GPU. We can see that its true as Pentium D(3.2/2.8GHz comparison) offers 81.3% scaling, and Athlon X2(2.4/2.2GHz) offers 63.7%.

Conclusion?? The scaling rate is similar despite the beliefs that Barcelona scales much better. It doesn't. Barcelona scores used Geforce 8800GTX on 1024x768, while Core 2 Duo system used 2xX1900XTX on a 1600x1200 resolution. If anything, Core 2 Duo scales better.


Tape out date of Barcelona core is August 15, 2006: http://en.wikipedia.org/wiki/AMD_K10

Looking at that average tape out to shipping date is 12 months, Barcelona couldn't have come sooner even if they wanted to.

 

[IntelUser2000]

This explains why both AMD and Intel have stuck with what are essentially single FP units (although in some cases both cpu's can execute more than 1 FP operation per clock).

Athlons can do 2 FP per clock cycle with any instruction, while Core 2's non-SSE FP does less than 2 FP per clock cycle just like Pentium M, while they can do more with SSE.

But really, we don't care anymore about old x87 FP performance as so many programs depend on the vector units and SSE.

 

[Viditor]

Originally posted by: Phynaz



You have either confused yourself, or you don't know what tape-out is.

Either way, you can't get chips before tape-out, as you appear to claim above.

The term tape-out comes from when magnetic tapes were used to transfer data. When the design of a chip was complete it would be output to tape (tape-out), and then the tape sent to the fab.

As you can see, there's no way that a chip could be produced in Nov, and tape-out to occur in Dec/Jan. That's backwards from the way the process works.

I think you are confusing the sample chips from Nov with the rev A0 tapeout...
For example, there are already samples of Nehelam (not working yet of course, but they can test individual sections) at Intel, even though it hasn't taped out yet either...
The tape-out is a full mask set for the entire wafer, not just samples.

Usually, the companies start on something simple like SRAM samples using the new techniques. They then move on to successively more complex samples until they tape-out the rev A0 full mask set.

 

[Viditor]

Originally posted by: T2k

Originally posted by: Viditor
Considering that AMD has already demonstrated a 3 GHz Phenom, I think your estimate of Q2 may be a bit pessimistic...

Did they...?

Sorry, I thought this was common knowledge...if you just Google some of this stuff you'll find it fairly quickly. They demoed it back in July...
arstechnica

Remember that Shanghai is due in Q2/Q3 2008 (45nm Barcelona),

Is it...?[/quote]

Roadmap

"Shanghai: Code name for the 45-nanometer successor to Barcelona. The quad-core Shanghai will offer some architectural improvements over Barcelona, as well as 6MB of cache. To be released in mid-2008"

 

[Idontcare]

Originally posted by: Viditor

Originally posted by: Phynaz



You have either confused yourself, or you don't know what tape-out is.

Either way, you can't get chips before tape-out, as you appear to claim above.

The term tape-out comes from when magnetic tapes were used to transfer data. When the design of a chip was complete it would be output to tape (tape-out), and then the tape sent to the fab.

As you can see, there's no way that a chip could be produced in Nov, and tape-out to occur in Dec/Jan. That's backwards from the way the process works.

I think you are confusing the sample chips from Nov with the rev A0 tapeout...
For example, there are already samples of Nehelam (not working yet of course, but they can test individual sections) at Intel, even though it hasn't taped out yet either...
The tape-out is a full mask set for the entire wafer, not just samples.

Usually, the companies start on something simple like SRAM samples using the new techniques. They then move on to successively more complex samples until they tape-out the rev A0 full mask set.

You are confusing the taping-out of test modules and simplified reticles with the concept of product samples (not the same thing) and the tape-out necessary to generate samples. I worked at TI for over 10 years in SiTD, I know these things, but the proof should be obvious that you are confused given the amount of people here trying to help you.

For example at TI we had something which you would call a tape-out of SUN's 65nm ROCK processor...only neither SUN nor TI nor anyone else but you (to my knowledge) would call it a tape-out. To be sure, yes something had taped-out, even test reticles must be taped-out. But the product (ROCK in my example here) was not what taped-out.

Same thing with Niagara2, earlier test modules were called Cornerstone NOT Niagara2. Yes cornerstone taped out, that was a test vehicle for some logic modules in Niagara2, but NO ONE would have called the taping out of Cornerstone to be "OMG did you here Niagara2 just taped out!"

When a company announces they are "sampling" a product name, that requires the product to have taped-out.

To my knowledge and first-hand experience at the heart of the industry this is how everyone intends to use the terminology. For >10yrs prior to today I have never heard the terms tape-out and sampling so mangled as you have here in this thread. Sorry you did not want to take my hint in my earlier posting above.

 

[Acanthus]

Originally posted by: Viditor

Originally posted by: cmdrdredd

Originally posted by: Viditor

Originally posted by: bryanW1995
amd has definitely made up some ground with (finally!) their release of barcelona, but they are going to lose some of it back before phenom is more than a couple of months old when penryn comes out. I think that the best amd can hope for is great scaling and a 3 ghz chip by Q2 08. Both very optimistic but certainly at least possible. Let's just say that the chips scale so well that we see an overal 15 % clock for clock advantage for phenom over penryn, that means that intel would need a 3.45 ghz penryn to match phenom. Penryn is going to release at 3.33, so it's reasonable to assume that they could easily ramp up to 3.5 or 3.66 in a hurry if necessary by Q2 08, but even if they couldn't, nehalem is going to paste both penryn AND phenom in 2H 08. The best that we consumers can hope for is for amd to be so competitive that intel pushes out nehalem as fast as possible. I personally think that penryn will be so dominant that nehalem will get delayed until 09.

Considering that AMD has already demonstrated a 3 GHz Phenom, I think your estimate of Q2 may be a bit pessimistic...
Remember that Shanghai is due in Q2/Q3 2008 (45nm Barcelona), which says to me that AMD will be binning the Agena at higher than they normally would for launch to make way for another product change by then.

1chip that is hand selected is alot different than getting thousands of them out in the market.

True, but you're making the assumption that yields are poor. If you go through Hector's more recent interviews where he admits the problems of Barcelona's tardiness, he is quite adamant about the fact that it was a design issue with rev B0, and not a yield or binning issue. If that is indeed the case, then there's no reason to assume that 3 GHz won't be available in production quantities on the newer rev.
It's true that there's no evidence either way, but most everyone with "inside connections" has been indicating that Phenom will be clocked VERY high (at least quite near the 3 GHz mark) on release...take it for what you will.

You tend to think that when a product is a year late.

 

[Viditor]

Originally posted by: Idontcare

Originally posted by: Viditor

Originally posted by: Phynaz



You have either confused yourself, or you don't know what tape-out is.

Either way, you can't get chips before tape-out, as you appear to claim above.

The term tape-out comes from when magnetic tapes were used to transfer data. When the design of a chip was complete it would be output to tape (tape-out), and then the tape sent to the fab.

As you can see, there's no way that a chip could be produced in Nov, and tape-out to occur in Dec/Jan. That's backwards from the way the process works.

I think you are confusing the sample chips from Nov with the rev A0 tapeout...
For example, there are already samples of Nehelam (not working yet of course, but they can test individual sections) at Intel, even though it hasn't taped out yet either...
The tape-out is a full mask set for the entire wafer, not just samples.

Usually, the companies start on something simple like SRAM samples using the new techniques. They then move on to successively more complex samples until they tape-out the rev A0 full mask set.

You are confusing the taping-out of test modules and simplified reticles with the concept of product samples (not the same thing) and the tape-out necessary to generate samples. I worked at TI for over 10 years in SiTD, I know these things, but the proof should be obvious that you are confused given the amount of people here trying to help you.

For example at TI we had something which you would call a tape-out of SUN's 65nm ROCK processor...only neither SUN nor TI nor anyone else but you (to my knowledge) would call it a tape-out. To be sure, yes something had taped-out, even test reticles must be taped-out. But the product (ROCK in my example here) was not what taped-out.

Same thing with Niagara2, earlier test modules were called Cornerstone NOT Niagara2. Yes cornerstone taped out, that was a test vehicle for some logic modules in Niagara2, but NO ONE would have called the taping out of Cornerstone to be "OMG did you here Niagara2 just taped out!"

When a company announces they are "sampling" a product name, that requires the product to have taped-out.

To my knowledge and first-hand experience at the heart of the industry this is how everyone intends to use the terminology. For >10yrs prior to today I have never heard the terms tape-out and sampling so mangled as you have here in this thread. Sorry you did not want to take my hint in my earlier posting above.

If you are correct, then I do have some humble pie to eat (and a couple of AMD and Intel Engineers to spank as they are the ones who told me this!).
To be clear, you are saying that tape out of A0 occured in November, and samples from that tape out arrived in January, yes?

BTW, next time don't worry about hints...I'm pretty thick-skinned and the information is far more valuable to me than my pride. This explanation was excellent!

One other thing...as IntelUser pointed out, Barcelona taped out in August last year. Since AMD fully expected to start shipping with rev B0 in March/April for a May/June launch, that would make the lead time closer to 8-9 months for Barcelona...just a thought. Too bad the design problems gave them the long delay (I think Hector called it a 6 month delay)!

 

[Nemesis 1]

Originally posted by: Viditor

Originally posted by: Idontcare

Originally posted by: Viditor

Originally posted by: Phynaz



You have either confused yourself, or you don't know what tape-out is.

Either way, you can't get chips before tape-out, as you appear to claim above.

The term tape-out comes from when magnetic tapes were used to transfer data. When the design of a chip was complete it would be output to tape (tape-out), and then the tape sent to the fab.

As you can see, there's no way that a chip could be produced in Nov, and tape-out to occur in Dec/Jan. That's backwards from the way the process works.

I think you are confusing the sample chips from Nov with the rev A0 tapeout...
For example, there are already samples of Nehelam (not working yet of course, but they can test individual sections) at Intel, even though it hasn't taped out yet either...
The tape-out is a full mask set for the entire wafer, not just samples.

Usually, the companies start on something simple like SRAM samples using the new techniques. They then move on to successively more complex samples until they tape-out the rev A0 full mask set.

You are confusing the taping-out of test modules and simplified reticles with the concept of product samples (not the same thing) and the tape-out necessary to generate samples. I worked at TI for over 10 years in SiTD, I know these things, but the proof should be obvious that you are confused given the amount of people here trying to help you.

For example at TI we had something which you would call a tape-out of SUN's 65nm ROCK processor...only neither SUN nor TI nor anyone else but you (to my knowledge) would call it a tape-out. To be sure, yes something had taped-out, even test reticles must be taped-out. But the product (ROCK in my example here) was not what taped-out.

Same thing with Niagara2, earlier test modules were called Cornerstone NOT Niagara2. Yes cornerstone taped out, that was a test vehicle for some logic modules in Niagara2, but NO ONE would have called the taping out of Cornerstone to be "OMG did you here Niagara2 just taped out!"

When a company announces they are "sampling" a product name, that requires the product to have taped-out.

To my knowledge and first-hand experience at the heart of the industry this is how everyone intends to use the terminology. For >10yrs prior to today I have never heard the terms tape-out and sampling so mangled as you have here in this thread. Sorry you did not want to take my hint in my earlier posting above.

If you are correct, then I do have some humble pie to eat (and a couple of AMD and Intel Engineers to spank as they are the ones who told me this!).
To be clear, you are saying that tape out of A0 occured in November, and samples from that tape out arrived in January, yes?

BTW, next time don't worry about hints...I'm pretty thick-skinned and the information is far more valuable to me than my pride. This explanation was excellent!

One other thing...as IntelUser pointed out, Barcelona taped out in August last year. Since AMD fully expected to start shipping with rev B0 in March/April for a May/June launch, that would make the lead time closer to 8-9 months for Barcelona...just a thought. Too bad the design problems gave them the long delay (I think Hector called it a 6 month delay)!

Outstanding! Tips hat.

 

[Viditor]

Originally posted by: Acanthus

You tend to think that when a product is a year late.

And it's an understandable assumption...just keep in mind that it's NOT the only plausible explanation, a design problem is equally plausible. Considering that design error is exactly what AMD has stated has happened, I personally consider it the more likely reason...but skepticism is perfectly reasonable here.

 

[Viditor]

Just thought I'd add some more grist for the mill here...
Kris Kubicki Blog

Production Barcelona samples come with the BA revision designator. These processors, manufactured after work-week 30 (WW30 for those who work in the corporate world) include errata fixes not present in the chips reviewed on September 10th.

One AMD developer, who wished to remain anonymous for non-disclosure purposes, stated, "B1 versus BA should be at least a 5%, if not more, gain in stream, integer and FPU performance."

An AMD engineer, when confronted with the claim, stated that 5% gains when moving from B1 to BA processors "seem conservative."

 

[zach0624]

Originally posted by: Viditor
Just thought I'd add some more grist for the mill here...
Kris Kubicki Blog

Production Barcelona samples come with the BA revision designator. These processors, manufactured after work-week 30 (WW30 for those who work in the corporate world) include errata fixes not present in the chips reviewed on September 10th.

One AMD developer, who wished to remain anonymous for non-disclosure purposes, stated, "B1 versus BA should be at least a 5%, if not more, gain in stream, integer and FPU performance."

An AMD engineer, when confronted with the claim, stated that 5% gains when moving from B1 to BA processors "seem conservative."

This will be very interesting regarding phenom's performance since it will be running on something like a b2 or b3(I haven't read much about steppings for a while so feel free to correct me if I'm wrong). Although this probably will end up like all the other info from amd and be BS. I really hope that is true though because, lets face it if amd goes down we will a be screwed.
Please AMD your our only hope.(sorry bad star wars joke)

 

[Viditor]

Originally posted by: zach0624

Originally posted by: Viditor
Just thought I'd add some more grist for the mill here...
Kris Kubicki Blog

Production Barcelona samples come with the BA revision designator. These processors, manufactured after work-week 30 (WW30 for those who work in the corporate world) include errata fixes not present in the chips reviewed on September 10th.

One AMD developer, who wished to remain anonymous for non-disclosure purposes, stated, "B1 versus BA should be at least a 5%, if not more, gain in stream, integer and FPU performance."

An AMD engineer, when confronted with the claim, stated that 5% gains when moving from B1 to BA processors "seem conservative."

This will be very interesting regarding phenom's performance since it will be running on something like a b2 or b3(I haven't read much about steppings for a while so feel free to correct me if I'm wrong). Although this probably will end up like all the other info from amd and be BS. I really hope that is true though because, lets face it if amd goes down we will a be screwed.
Please AMD your our only hope.(sorry bad star wars joke)

AMD hasn't given out any BS, they just weren't able to fulfill the promise of a launch with the first stepping (B0)...in other words they screwed up.
That said, you are essentially correct...
Here's the list:

Stepping B0 - The first Barcelona benchmarked back in April...VERY broken and couldn't even clock over 1.6 GHz

Stepping B1 - This is the engineering sample chip given to reviewers and the one with all of the benches we've been reading. These are low and mid power Barcelonas (Opterons)

Stepping BA - This is the actual production Barcelona now shipping and available in stores. It is supposedly at least 5% faster than B1 with many errata fixed. Again, mid and low powered Barcelonas

Stepping B2 - Engineering sample version of High Performance Barcelonas. The 2.5 GHz Barcelona sample was one of these...

Stepping B3 - At the moment, this is reputed to be the actual shipping version of the high powered Barcelona, due to ship in Nov and be available in Dec.

Edit: BTW, the person Kris mentions as saying BA is 5%+ faster was an AMD Developer, not an employee...in other words, a 3rd party company man who is under NDA.

 

[intangir]

Originally posted by: Viditor

Originally posted by: Idontcare

To my knowledge and first-hand experience at the heart of the industry this is how everyone intends to use the terminology. For >10yrs prior to today I have never heard the terms tape-out and sampling so mangled as you have here in this thread. Sorry you did not want to take my hint in my earlier posting above.

If you are correct, then I do have some humble pie to eat (and a couple of AMD and Intel Engineers to spank as they are the ones who told me this!).
To be clear, you are saying that tape out of A0 occured in November, and samples from that tape out arrived in January, yes?

BTW, next time don't worry about hints...I'm pretty thick-skinned and the information is far more valuable to me than my pride. This explanation was excellent!

One other thing...as IntelUser pointed out, Barcelona taped out in August last year. Since AMD fully expected to start shipping with rev B0 in March/April for a May/June launch, that would make the lead time closer to 8-9 months for Barcelona...just a thought. Too bad the design problems gave them the long delay (I think Hector called it a 6 month delay)!

I would venture to say that you misinterpreted what your AMD/Intel contacts told you, as I find it hard to believe they could get this wrong. Idontcare and Phynaz are correct. It is impossible to have product samples manufactured without the masks that taping out produces. And that implies that the chip project feels that the design is finished, barring feedback that only real silicon can provide, since design masks are expensive things (I think they're in the neighborhood of 6 figures?). This is pretty basic knowledge in the semiconductor industry.

Basically, to have Penryn silicon booting up in January, tape-out must have occurred 2-3 months beforehand. There generally are several respins of the masks before actual volume manufacturing to fix bugs found in post-silicon debug work and to make tweaks for yield and speed, but only the first masks produced are referred to as the tape-out milestone.

This is not to say that AMD could not have made test runs of cache structures and other circuits to test their manufacturing process and design parameters. But these test vehicles could not be considered Barcelona samples.

AMD announced Barcelona's tapeout on Aug 15, 2006.

The Inquirer posted the first pictures of Barcelona wafers on Sep 29, 2006. Of course, those aren't samples yet. You have to cut the dies from the wafers, and then comes the packaging step, mounting the silicon die in an assembly that you can plug into a motherboard, before you get a usable chip. This may be done on the other side of the world from where the wafer is actually manufactured.

So, summary: first silicon samples necessarily come months AFTER tapeout.

 

[Viditor]

Originally posted by: intangir


I would venture to say that you misinterpreted what your AMD/Intel contacts told you, as I find it hard to believe they could get this wrong.

Yes and no...they also misspoke (which is why they deserve the spanking as much as I do). They told me in an e-mail that Penryn was taping out at the end of December...
The sad part is that I did know all of this (which is why when IDontCare spelled it out in his post, the light finally clicked on), but I was blindly going by the e-mail without thinking it through and trying to rectify the 2 positions...sigh...mea culpa.
[/quote]

 

[dasdas]

All of the talks /posts I have seen on barcelona/phenom performance so far miss a very important aspect of the native quad core's architecture. AMD can now go from quad core to octal core in a blink using intel's approach that is stitching two physical chips on one die and I am sure Intel is having nightmares on this and HT connect will make it even more easier. Barcelona might be tad slower right now, but when comes the time of B3-B4 stepping amd will be ready to make octal core cpus and they will for sure have the first octal chip in the market. Intel will have to some how put 4 physical C2d in one dye and due to FSB saturation and heat issues they wont be able to do it as far as I know, might be possible with penryn but not sure.

Amd have passed a big engineering hurdle by having working native quad core chip and intel will agree, as I read somewhere recently that one of the top Intel executive said its not easy to implement a native quadcore chip. I am sure by Q2 2008 will see the first octal chip may be earlier and amd should be able to capture lots of lost ground specially in the server market. And I am also very certain that this is the reason Intel went to 45nm so quickly.

After all if I have a choice of getting a quad core q6600 or a dual core x6850 I will choose q6600 its just human nature for ppl like me ... so when given the choice of having a tad slower octal core as compared to faster quad core I will go for octal core chip specially when it will fit my current motherboard ( It is rumored that octal core Barcelona/shanghai will fit socket F ) .

 

[Viditor]

Originally posted by: dasdas
All of the talks /posts I have seen on barcelona/phenom performance so far miss a very important aspect of the native quad core's architecture. AMD can now go from quad core to octal core in a blink using intel's approach that is stitching two physical chips on one die and I am sure Intel is having nightmares on this and HT connect will make it even more easier. Barcelona might be tad slower right now, but when comes the time of B3-B4 stepping amd will be ready to make octal core cpus and they will for sure have the first octal chip in the market. Intel will have to some how put 4 physical C2d in one dye and due to FSB saturation and heat issues they wont be able to do it as far as I know, might be possible with penryn but not sure.

Amd have passed a big engineering hurdle by having working native quad core chip and intel will agree, as I read somewhere recently that one of the top Intel executive said its not easy to implement a native quadcore chip. I am sure by Q2 2008 will see the first octal chip may be earlier and amd should be able to capture lots of lost ground specially in the server market. And I am also very certain that this is the reason Intel went to 45nm so quickly.

After all if I have a choice of getting a quad core q6600 or a dual core x6850 I will choose q6600 its just human nature for ppl like me ... so when given the choice of having a tad slower octal core as compared to faster quad core I will go for octal core chip specially when it will fit my current motherboard ( It is rumored that octal core Barcelona/shanghai will fit socket F ) .

Doing that is a LOT harder than it sounds, or we would have seen MCM quad core Opterons 6 months ago. Hector even stated that AMD just couldn't afford the R&D to develop a brand new MCM (though most everyone at AMD was lamenting that fact...).
AMD already has a chip called Sandtiger with native 8-16 cores on the Roadmap for release in 2009...
Roadmap

 

[dasdas]

The main reason AMD couldnt do it with K8 because they were well in on their way with the original k10 project which had to be scrapped and instead they had to start the K8L ( Barcelona) project from scratch and were in extreme pressure to finish it in a limited time span. Given the k8 architecture, fusing two k8s is not that difficult at all IMHO.

 

[Viditor]

Originally posted by: dasdas
The main reason AMD couldnt do it with K8 because they were well in on their way with the original k10 project which had to be scrapped and instead they had to start the K8L ( Barcelona) project from scratch and were in extreme pressure to finish it in a limited time span. Given the k8 architecture, fusing two k8s is not that difficult at all IMHO.

Well, I think you have a few of those mixed up...
Barcelona is K10, and K8L is (supposedly) the mobile X2 Turion (K8L was a low power chip).
But for the K8 or K10 design, it's actually much harder...remember that you essentially have a nortbridge on each core, but you only have enough access to one of them in the socket. I'm sure something could be developed, but it certainly wouldn't be easy or cheap, and would almost certainly require a different socket.
Nor would it be as much of an improvement...
Remember that AMD's architecture is much more latency sensitive than Intel's...

 

[jones377]

Originally posted by: Viditor

Originally posted by: intangir


I would venture to say that you misinterpreted what your AMD/Intel contacts told you, as I find it hard to believe they could get this wrong.

Yes and no...they also misspoke (which is why they deserve the spanking as much as I do). They told me in an e-mail that Penryn was taping out at the end of December...
The sad part is that I did know all of this (which is why when IDontCare spelled it out in his post, the light finally clicked on), but I was blindly going by the e-mail without thinking it through and trying to rectify the 2 positions...sigh...mea culpa.

[/quote]

Is anyone seriously buying this?

 

[JackPack]

Originally posted by: dasdas
AMD can now go from quad core to octal core in a blink using intel's approach that is stitching two physical chips on one die and I am sure Intel is having nightmares on this and HT connect will make it even more easier.

An octo-core MCM is physically impossible with Barcelona. AMD did not layout Barcelona for an MCM design.

Study a photo of an unlidded Barcelona and then return to this thread.

 

[Keysplayr]

Originally posted by: dasdas
The main reason AMD couldnt do it with K8 because they were well in on their way with the original k10 project which had to be scrapped and instead they had to start the K8L ( Barcelona) project from scratch and were in extreme pressure to finish it in a limited time span. Given the k8 architecture, fusing two k8s is not that difficult at all IMHO.

Semi companies run many projects in parallel, although start and finish times differ. Example would be Intel. While working on Penryn and Nehalem, they still came out with a quad core Kentsfield. And by the way, I don't believe the native quad core Barcelona is a modular design where they could add or subract cores at will. So the only thing AMD could do in a "blink" is, well, blink.

 

[Bateluer]

I think we'll see a strong showing with Phenom, provided its priced competitively. The benchmarks for Penryn with extremely underwhelming and the benchmarks for Barcelona were promising.

Will a 2Ghz Phenom beat the QX6850? No, its too expensive for most anyway. Will the 2Ghz Phenom outperform the CPUs its priced against? Likely.

 

[gOJDO]

IMO, if Intel are not going to release a Q6400 then the best bang for the buck of all desktop quadcore CPUs will be the Q6600.

I am 100% sure that Phenom won't catch up the performance of highest clocked Kentsfield. Phenom's performance will be attractive for those who love folding, but for general user and the rest Core2 will be the way to go.
Also, I am pretty convinced that Penryn will only widen the performance gap between Intel and AMD. On the desktop it will own K10 more than Core2 owned K8.