I dont have the numbers at hand right now but if i remember correctly GloFos 28nm is a little better than TSMC 28nm both in density and electrical.
I'm pretty sure, but not 100% confident, that TSMC's HKMG process is superior* in terms of electrical parametrics to GF's HKMG process.
GF wins on density (gate first does that, no one argues otherwise), and with their desire to sell wafers and take a lower margin in the process they certainly win out on price.
* the topic of "superior" when it comes to electrical performance is one that can be quite confusing to people who have little or no background in EE, IC design, or process node development (I am not saying you don't, just saying I am sure there are folks reading this thread who may fall into that category).
So...when I speak of one node being superior to another I am generally thinking of the case where we normalize all the drive currents and leakages observed when one is comparing transistors of the exact same width (not length), at the same operating temperature, the same operating voltage, and the same lifetime-reliability.
For example, take a given (arbitrary) circuit and implement it in GF's 28nm and TSMC's 28nm. Put it at 1V, on a hot-plate heated to 105C, and clock how fast it goes.
At the same density (same xtor width's for the xtors in the circuit), TSMC's is going to clock faster. Alternatively you could clock it the same as the GF circuit by lowering the voltage, now it clocks just as fast but consumes less electricity. Alternatively you could keep the same voltage but shrink the circuit (smaller xtor width) itself which until you reach the same clockspeed. Etc.
In all these ways the TSMC process is superior to the GF process because of one reason, it is gate-last so it has an automatic (unavoidable) benefit to the drive current that gate-first doesn't provide (can't provide).
There are good reasons to go with gate-first, but they generally entail lowering production cost (higher max densities, albeit at the expense of drastically lower clocks and performance on a normalized* basis) and are not pursued for the purposes of delivering superior electrical parametrics.
(tl;dr - there is a darn good reason why no one on earth will have a gate-first process, including IBM and GF, come 20nm )