Perhaps i remember the numbers for GloFos 28nm HKMG SOI(PD). I will say that for 28nm Bulk you will be correct.
And here comes the big BANG,
I strongly believe that if Kaveri is BULK, then it will be produced at TSMC.
I'm pretty sure, but not 100% confident, that TSMC's HKMG process is superior* in terms of electrical parametrics to GF's HKMG process.
GF wins on density (gate first does that, no one argues otherwise), and with their desire to sell wafers and take a lower margin in the process they certainly win out on price.
* the topic of "superior" when it comes to electrical performance is one that can be quite confusing to people who have little or no background in EE, IC design, or process node development (I am not saying you don't, just saying I am sure there are folks reading this thread who may fall into that category).
So...when I speak of one node being superior to another I am generally thinking of the case where we normalize all the drive currents and leakages observed when one is comparing transistors of the exact same width (not length), at the same operating temperature, the same operating voltage, and the same lifetime-reliability.
For example, take a given (arbitrary) circuit and implement it in GF's 28nm and TSMC's 28nm. Put it at 1V, on a hot-plate heated to 105C, and clock how fast it goes.
At the same density (same xtor width's for the xtors in the circuit), TSMC's is going to clock faster. Alternatively you could clock it the same as the GF circuit by lowering the voltage, now it clocks just as fast but consumes less electricity. Alternatively you could keep the same voltage but shrink the circuit (smaller xtor width) itself which until you reach the same clockspeed. Etc.
In all these ways the TSMC process is superior to the GF process because of one reason, it is gate-last so it has an automatic (unavoidable) benefit to the drive current that gate-first doesn't provide (can't provide).
There are good reasons to go with gate-first, but they generally entail lowering production cost (higher max densities, albeit at the expense of drastically lower clocks and performance on a normalized* basis) and are not pursued for the purposes of delivering superior electrical parametrics.
(tl;dr - there is a darn good reason why no one on earth will have a gate-first process, including IBM and GF, come 20nm )
http://www.anandtech.com/show/4444/amd-llano-notebook-review-a-series-fusion-apu-a8-3500m
AMD Llano released in June 2011 manufactured on GF 32nm SOI. by the time Kaveri releases in early 2014 it would be 2.5 years to replace 32nm high performance SOI with 28nm high performance bulk process. for a half node thats the worst delay you can expect. Do you believe AMD would not have moved to 28nm bulk process if GF could get a 28nm bulk process with high k metal gates in volume production for Q4 2012. instead now it will happen in Q4 2013. the reason is GF 28nm was badly delayed. The very fact that AMD had to cook up Richland which was a clock bumped Trinity points to delays at GF 28nm.
Feb 2012 roadmap
http://images.anandtech.com/doci/5503/Screen Shot 2012-02-01 at 2.14.03 PM.png
Jan 2013 roadmap
http://images.anandtech.com/doci/6567/AMD-024.jpg
did you forget that Kaveri was revealed to public as early as Feb 2012 to be made on 28nm bulk and internally AMD must have decided even before. Once AMD knew how badly GF had screwed up 28nm they scrambled to change their roadmap with Richland and tried marketing it as though that was the plan from the start.
As far as GF is concerned they have been all talk. Until 20nm products fabbed at GF reach the market everyone should take their statements with a huge mountain of salt.
Perhaps i remember the numbers for GloFos 28nm HKMG SOI(PD). I will say that for 28nm Bulk you will be correct.
And here comes the big BANG,
I strongly believe that if Kaveri is BULK, then it will be produced at TSMC.
so what are those sizes? Hate to see people try to debunk one another and not provide evidence without having to sleuth yourself.
Bobcat is TSMC 40nm and Llano is GloFo 32nm, not the same.
Okay, but if the same sort of SIMDs are similarly sized between the two you don't think that says something about density
Nop, because one design may use larger transistors in order to have higher performance. That is, you may use larger sized transistors at 32nm that will give you higher performance(higher clocks) and have the same die area as with 40nm. But that doesnt mean they have the same density.
As of the last update, Kaveri is still 28nm Bulk HKMG from Global Foundries. Looking at the various "movements/delays" news coming up I can confidently say it is GloFo .See my post above,
I strongly believe that IF kaveri is 28nm bulk it will be at TSMC and not GloFo. And that because of what IDC said in his post above.
Also,
Because GloFo had only a single Fab for 32nm HKMG SOI, the same Fab also produces 65nm and 45nm, they couldn't increase 28nm bulk volumes earlier. Not only that, but if 28nm Bulk has worst or even equal Electrical characteristics than 32nm HKMG SOI then i dont see any reason for AMD to be in a harry to use it. I believe it is the reason they will not produce Server parts at 28nm and they will continue with 32nm HKMG SOI for a third year.
32nm HKMG SOI today must be extremely cheap, with very high yields and same or better electrical characteristics than 28nm Bulk. The only advantage GloFos 28nm Bulk has over 32nm is higher density.
Will have to wait and see where Kaveri will be produced.
I'm not aware of the public existence of any Cayman die shots (nor Cypress).
There's a Barcelona die shot meshed with R770, but it's not actually Cayman:
Silly AMD...
Well if I can't bake my dead HD 6950 back into life, maybe I can take some die shots.Okay this is looking annoying, yeah.
So I guess that means no RV740 die shot either..
I wonder if it's worth trying to estimate anything from size differences between different models :/
That's not 100% correct, STM's FDSOI@20nm, which will be produced at GF's fab will be GateFirst. But I also wonder if that decision would be its deathblow.
3) Allow your marketing team to insist the silicon die gets laser etched to kingdom-come and back, absolutely undermining the thermal conductivity of the interface and ensuring your 28nm semi-custom IC will run warmer and use more power because of it. Check. (and facepalm)
1) Pay oodles of money to have AMD design semi-custom logic IC for your most advanced gaming console ever. Check.
2) Pay oodles of money to have TSMC fab your semi-custom logic IC on the most advanced 28nm HKMG node available for mass production. Check.
3) Allow your marketing team to insist the silicon die gets laser etched to kingdom-come and back, absolutely undermining the thermal conductivity of the interface and ensuring your 28nm semi-custom IC will run warmer and use more power because of it. Check. (and facepalm)
I guess you are right, but it is not only STM's blitz, it is mostly the whole SOI-Consortium. There is no other SOI process besides IBM and that is probably not enough to pay off all the Soitec workers, STM's development engineers, university institutes etc. pp. I got the impression that there is half or a whole industry at risk in middle/southern France.In other words, I take the very fact the layperson has been made aware of STM's FDSOI thanks to STM's marketing blitz to mean STM is suffering from a "customer confidence crisis" and they have zero (or maybe just one or two small volume customers) signed up to tapeout on their 20nm FDSOI node...so they are in panic mode to get customers.
FDSOI has no long term viability.
A QR code on the die. Do I get an achievement (void your warranty 100G) if scan it with Kinect?
I think, noise was the driver for this size.4) Design huge case and air conditioning system to take care of all this heat Check
Would be funny if that's (also) why X1 is so big comparatively
I just did a little internet reseach about Gfirst <> GLast and I wonder about one thing; can the thin SOI-film help them in the difficulties encountered at 20nm and GateFirst?STM's process, while exotic and cool, is far from being a high-volume mass production type node.
You call that long term?Very adventurous belief , expect FDSOI to be used at 28 and 20nm.