xBox One's SoC is TSMC

[Homeles]

You are confusing PDSOI with FDSOI.

I actually dropped a pretty massive hint in that post, and the both of you have managed to completely miss it. Can't say I'm surprised.

 

[Idontcare]

I just did a little internet reseach about Gfirst <> GLast and I wonder about one thing; can the thin SOI-film help them in the difficulties encountered at 20nm and GateFirst?
Just now I have the impression that they are rather crazy, but maybe I just overlooked a nice side-effect of FDSOI?

I somehow feel sympathy for them, trying to do things the hard way and not following the crowd, but in the worst case they really are just crazy :ninja:

In general, companies that opt to go gate-first instead of gate-last are companies who simply don't have the resources necessary to make a production-worthy gate-last integration scheme on the timeline necessary for such a node to be relevant to the market when it finally comes out.

It is no different than the staggered introduction timeline (by node) for the industry's transition from aluminum to copper, or single-damascene to dual-damascene, or wet-etch back to CMP, or SiON gates to HKMG (be they gate first or gate last), or strain engineering in the channel...the list goes on and on.

There are key skills and competencies in terms of engineering and process know-how that must be available, internally, to the R&D team if they are going to be able to reliably and competently capture the risks and surmount the challenges that comes with the integration of these new features.

A team which lacks key skill in one area will find itself doing unusual (to the industry norm or expectation) things in its process integration scheme to essentially compensate for the intrinsic weaknesses in its own team.

(really no different than countries at war in which the generals have no choice but to go to war with the soldiers they have, which won't necessarily be the ones they want to have, and change their war strategies to mask the weaknesses while leveraging the strengths of their nation's war machine)

For specific example, to master gate-last integration you must have an absolutely top-notch CMP R&D engineering team. If you do not have a handle on your CMP processes, mastering the issues of dishing vs erosion vs yields vs process time vs corrosion vs etc, then your efforts to develop a gate-last process will be fruitless as the transistor variability will be all over the map, within die and across wafer.

In a lot of ways the decisions that get made regarding process flow literally come down to the strengths and weaknesses of specific people involved in the development of the processes themselves.

And in that sense what the process integration team is doing is they are not opting out of specific paths based on the technical benefits or tradeoffs of those paths, but rather they are essentially "engineering out" the weakest link in the R&D team personnel-wise.

(personal experience note - at TI we were the only IDM to resort to using a single-damascene copper BEOL for 90nm, versus everyone else using the preferred dual-damascene integration flow. Why? Because the ECD chemistry for bottom-up filling with copper was one of those processes which required exquisite skill and capability and it just so happened to be one of our weaknesses at the time - so the process flow integration team opted for the less-risky path of single-damascene so as to avoid the possibility of having extended delays in getting 90nm released to production. BTW an excellent publicly available document on dual-damascene integration, complete with real industry data can be found here)

 

[Fjodor2001]

363mm2 = ~156 dies per 300mm wafer

with 80% yields = ~124 dies

Lets assume that TSMC sells each wafer at $3000

3000/124 = ~$24.019 per die

Haswell 4C GT2 is 1.4B transistors, i.e. about 1/3 of the 5B XBONE SoC transistors!

http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/5

So basically you could make a 12C Haswell with 3x the amount of EUs in GT2 for about $24 ? :awe: Not taking into account 22 nm vs 28 nm aspects of course...

Also, isn't it strange that we have:

XBONE: 363 mm2, 5B transistors, 28 nm => 13.7M transistors/mm2.
Haswell 4C GT2: 177 mm2, 1.4B transistors, 22 nm => 7.9M transistors/mm2.

Shouldn't the transistor count per mm2 be higher for Haswell @ 22 nm compared to XBONE @ 28 nm?

 

[Enigmoid]

Haswell 4C GT2 is 1.4B transistors, i.e. about 1/3 of the 5B XBONE SoC transistors!

http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/5

So basically you could make a 12C Haswell with 3x the amount of EUs in GT2 for about $24 ? :awe: Not taking into account 22 nm vs 28 nm aspects of course...

Also, isn't it strange that we have:

XBONE: 363 mm2, 5B transistors, 28 nm => 13.7M transistors/mm2.
Haswell 4C GT2: 177 mm2, 1.4B transistors, 22 nm => 7.9M transistors/mm2.

Shouldn't the transistor count per mm2 be higher for Haswell @ 22 nm compared to XBONE @ 28 nm?

Density is different between logic and eSRAM.

CPU and GPUs also have different densities.

Ex) GK107 @ 1.3B tranistors and 118 mm^2. (11 M transistors per mm^2)

 

[Saylick]

Also, isn't it strange that we have:

XBONE: 363 mm2, 5B transistors, 28 nm => 13.7M transistors/mm2.
Haswell 4C GT2: 177 mm2, 1.4B transistors, 22 nm => 7.9M transistors/mm2.

Shouldn't the transistor count per mm2 be higher for Haswell @ 22 nm compared to XBONE @ 28 nm?

There are a couple other people on this forum who can probably answer your question at a deeper level, but here's my take:

1) A good chunk of the 5B transistors in the XBO are for the GPU and the eSRAM, both of which add a lot to the total number of transistors but do not take up a lot of space.

2) From what I hear, Intel engineers lays out the circuitry on performance critical sections (e.g. the cores) by hand, which is less area efficient than letting a computer do the work of packing the transistors.

3) Additionally, if you were to compare the amount of die space dedicated to the CPU vs. the GPU, there is a lot more die space dedicated to the CPU on Haswell than the die space for the Jaguar cores for XBO.

 

[Fjodor2001]

--

 

[PPB]

Haswell 4C GT2 is 1.4B transistors, i.e. about 1/3 of the 5B XBONE SoC transistors!

http://www.anandtech.com/show/7003/the-haswell-review-intel-core-i74770k-i54560k-tested/5

So basically you could make a 12C Haswell with 3x the amount of EUs in GT2 for about $24 ? :awe: Not taking into account 22 nm vs 28 nm aspects of course...

1°: stacking dies together is not useful for comparisons, so we dont know how many HWL cores and how many EUs would fit into that 5bn transistor budget if we ignore interconects, extra hardware added for dedicated porpuses, etc.

2°: Nevermind, in the bolded part you just admitted the comparation was pointless.

Also, isn't it strange that we have:

XBONE: 363 mm2, 5B transistors, 28 nm => 13.7M transistors/mm2.
Haswell 4C GT2: 177 mm2, 1.4B transistors, 22 nm => 7.9M transistors/mm2.

Shouldn't the transistor count per mm2 be higher for Haswell @ 22 nm compared to XBONE @ 28 nm?

That's why you dont take transistor count numbers from PR slides at face value.

 

[Fjodor2001]

Ok, then let's go by die area instead. We have 177 mm2 for Haswell 4C GT2 vs 363 mm2 for XBONE SoC. Then we have 22 nm vs 28 nm, so at 28 nm Haswell would occupy about (28/22)^2=1.62 => 62% more die area. At 28 nm that would mean it should require about 177*1.62=287 mm2.

So a 4Cx1.5=6C Haswell with 1.5x the amount of GT2 EUs @ 28 nm would occupy about 1.5x287 mm2=430mm2, which is pretty close to the 363 mm2 XBONE SoC. So it ought to be possible to make a 6C Haswell with 1.5x the amount of GT2 EUs @ 28 nm for not much more than the XBONE SoC's $24 in pure production cost?

 

[Abwx]

Ok, then let's go by die area instead. We have 177 mm2 for Haswell 4C GT2 vs 363 mm2 for XBONE SoC. Then we have 25.8 nm vs 28 nm, so at 28 nm Haswell would occupy about (28/25.8)^2=1.375 => 37.5% more die area. At 28 nm that would mean it should require about 177*1.375 = 244 mm2.

So a 4Cx1.5=6C Haswell with 1.5x the amount of GT2 EUs @ 28 nm would occupy about 1.5x244 mm2=366mm2, which is pretty close to the 363 mm2 XBONE SoC. So it ought to be possible to make a 6C Haswell with 1.5x the amount of GT2 EUs @ 28 nm for not much more than the XBONE SoC's $24 in pure production cost?

Fixed the numbers....:biggrin:

 

[PPB]

Dont you dare downplay Intels mighty 22nm process, I wont allow you! :awe:

 

[Abwx]

Dont you dare downplay Intels mighty 22nm process, I wont allow you! :awe:

Lol , actualy it s intel s own numbers , although indirectly...

 

[Idontcare]

Also, isn't it strange that we have:

XBONE: 363 mm2, 5B transistors, 28 nm => 13.7M transistors/mm2.
Haswell 4C GT2: 177 mm2, 1.4B transistors, 22 nm => 7.9M transistors/mm2.

Shouldn't the transistor count per mm2 be higher for Haswell @ 22 nm compared to XBONE @ 28 nm?

xtor density will be highly dependent on target clockspeeds and the investment a company makes in terms of development cost for the IC.

You absolutely cannot look at xtor density and just assume it represents the best that could have been done for the design or the node, it doesn't work that way.

 

[SiliconWars]

Not all parts of the die scale equally either, I/O for example I believe on 22nm probably isn't a lot different from 28nm, so that will inflate die size.

That said, TSMC does appear to have extremely high density and this has been known for a while.

 

[Homeles]

That's why you dont take transistor count numbers from PR slides at face value.

I've got a better idea: Stop spreading FUD (that's Fear, Uncertainty and Doubt, since you probably didn't know), and educate yourself.

Do you not realize that the argument that you are making is that transistor density is solely based on the manufacturing process? You deserve to be humiliated for such an assertion.

Allow me to enlighten you: different circuits have different maximum densities. SRAM can be packed denser than logic. DRAM can be packed denser than SRAM. Here's an example:

This very fact is why we aren't running around with SRAM memory modules, despite SRAM's higher power efficiency and speed over DRAM.

Also, isn't it strange that we have:

XBONE: 363 mm2, 5B transistors, 28 nm => 13.7M transistors/mm2.
Haswell 4C GT2: 177 mm2, 1.4B transistors, 22 nm => 7.9M transistors/mm2.

Shouldn't the transistor count per mm2 be higher for Haswell @ 22 nm compared to XBONE @ 28 nm?

Since the person I've quoted above hasn't a damned clue what he's talking about, allow me to give you the correct answer. Saylick has already mentioned several truths, but the most significant one is going to be the first one he pointed out.

Case in point: AMD's Phenom II (Deneb) has a die size 258mm², and a transistor count of 758 million. Their Athlon II, which uses the same CPU architecture and same manufacturing process, has a die size of 117mm² and a transistor count of 234 million. If we take the number of transistors and divide it by the surface area of the die, we arrive at roughly 3 million transistors per mm² for Phenom II, and 2 million transistors per mm² for Athlon II.

Traditionally, over time, chip designers are able to extract better density out of a manufacturing process. However, here we're seeing 33% less density in the Athlon II, despite it launching 5 months later. Does that mean AMD's tried to pull a fast one on us, and lied about the transistor count of one or both of their processors? Unlike the tinfoil hatter above me would brilliantly assert, the answer is a resounding no.

Back to Athlon II vs. Phenom II: So if the process is the same, and the architecture is the same... why is there such a difference?

As Saylick hinted, GPUs typically have higher density than CPUs. He also hinted that SRAM has higher density than CPUs.

The reason why an Athlon II die has a significantly lower transistor density than a Phenom II die is because the Athlon II doesn't have an L3 cache. L3 cache typically uses 6 transistor SRAM, which is very dense compared to CPU logic. Coincidentally, the XBOX One's embedded RAM is SRAM, and if it is 6T SRAM like the Phenom II's L3 cache, that 32 MB SRAM cache contains roughly 1.6 billion transistors alone. That's just under a third of the transistors on the SoC.

Wonder how much area it takes up?

TSMC's 28nm process has a SRAM cell size of 0.130µm²/bit. This means ~7.692 million bits can fit in 1 mm². There are 2^28 bits in 32MB, so that leaves us with a die size of ~35mm², or ~54mm² with overhead. We get over 46 million transistors per square millimeter; compare that to the Athlon II's 2 million/mm².

Also, as IDC mentioned above, this is the theoretical best. Intel's 22nm node has a maximum 6T SRAM density of 0.092 µm²/bit, but their largest 22nm SRAM cells have a density of 0.130 µm²/bit, which coincidentally is the exact area of TSMC's maximum SRAM cell density.

 

[AtenRa]

You deserve to be humiliated for such an assertion.

I didnt know humiliation was allowed here in AT forums. D:

 

[ShintaiDK]

I didnt know humiliation was allowed here in AT forums. D:

I cant imagine technical humiliation would be disalllowed.

This thread is already filled with so much wrong.

 

[NostaSeronx]

SRAM can be packed denser than logic. DRAM can be packed denser than SRAM.

Isn't this because DRAM is 1T/2T where SRAM is 6T/8T?

 

[Fjodor2001]

I cant imagine technical humiliation would be disalllowed.

Correcting technical information does not mean it has to be done in a humiliating way.

In fact such an approach is often a trigger that spins the discussion into personal insults and flame wars, effectively destroying the technical discussion and thread itself if not stopped at an early stage.

 

[USER8000]

I think, noise was the driver for this size.

BTW, the 363 mm² die has much more area to dissipate it's heat than Vishera or Richland.

P.S.: My May die size estimation (377 mm²) was only off by 4% or 2% per dimension.

It also is still smaller than many higher end graphics chips too,and not much larger than the Nvidia GK104 or AMD Tahiti in overall surface area. Moreover,dual GPU cards probably kick out more heat anyway.

 

[Fjodor2001]

Based on what is known about the XBONE SoC, is it possible to estimate its TDP? At least what range it's likely to be within?

 

[jpiniero]

Based on what is known about the XBONE SoC, is it possible to estimate its TDP? At least what range it's likely to be within?

I'd say around 100. Might be more now that they raised the GPU clocks a bit.

 

[Homeles]

Isn't this because DRAM is 1T/2T where SRAM is 6T/8T?

Typically, yeah.

 

[PPB]

Poor guy, butthurt from another thread, still thinks he can still educate anyone in the rest. Just let it go

You cant take Transistor count from slides from the moment they can be wrong. Just when everybody was running numbers calculating density on AMD's new cpus and the initial number then was corrected, leaving everyone in the dark.

So please, stop trying to correct anyone. It was good for a laugh at first, but not anymore

 

[Homeles]

Poor guy, butthurt from another thread, still thinks he can still educate anyone in the rest. Just let it go

Aww, look at you trying to pass it off as if I'm the one who got the crap kicked out of them. You're so cute.

You cant take Transistor count from slides from the moment they can be wrong.

So can every report of transistor count.

Just when everybody was running numbers calculating density on AMD's new cpus and the initial number then was corrected, leaving everyone in the dark.

Oh no, people's comparisons that they were running for fun were no longer valid... it must be the end of the world...

So please, stop trying to correct anyone. It was good for a laugh at first, but not anymore

I'm not going to let you keep spreading ignorance. Want me to back off? Stop feigning that you are knowledgeable about these subjects.

Knock off all the insults
Markfw900
Ananadtech moderator.

 

[Tuna-Fish]

So it ought to be possible to make a 6C Haswell with 1.5x the amount of GT2 EUs @ 28 nm for not much more than the XBONE SoC's $24 in pure production cost?

More or less. The actual production cost of CPUs is pretty small. What costs big bucks is design, and keeping top-end foundry research going on.

Basically, you shouldn't think of CPU economics like fuel or something, where most of the cost of the product is direct cost of manufacture, but instead like a newspaper, where the cost to produce one more product is a minuscule fraction of price, but the cost to keep the design (content) current is why they can't be sold for cheaper.