lopri
Elite Member
- Jul 27, 2002
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The reason I was thinking about it is because I know that DMI is, as mentioned earlier, a PCIe x4 lane. (DMI = NB to SB interconnect on Intel chipsets) On the other hand, AMD uses HyperTransport for just about every interconnects (core to core, chip to chip) and it's an open standard - which is why NV has been using it on their Intel chipsets.Originally posted by: apoppin
How does nvidia - using their own pciE first developed for AMD platforms -Linkboost was introduced on nforce 590 for *AMD CPUs* - can possibly be "unfairly crippling" intels' own chip sets? Unless you want to take his argument to the extreme that intel's chipset engineer are also incompetents regarding PCIe ... i think not
With this information, it's easily explained the instability caused by high PCIe clocks if the DMI clock generator is shared with PCIe clock generator on Intel boards. Because basically this will mess up the NB-SB interconnect. Yeah but I need someone's confirmation on this. I don't know for sure.