Zen 2 based Raven Ridge and Pinnacle Ridge

[prtskg]

To get the terminology straight: https://en.wikipedia.org/wiki/List_of_Intel_CPU_microarchitectures#Roadmap

Tick: Process
Tock: Architecture (same process)

Thanks for the link.
I doubt Pinnacle Ridge is a refresh like kaveri to godavari. It'll be more like improvement from BD to Piledriver or Phenom I to Phenom II. That's how a new architecture is refined. Easy gains can still be made with zen and I expect AMD will take it, that's very logical. Zen is very competitive and i expect AMD will give it more importance than it gave BD.
Raven Ridge on the other hand seems very interesting. To be honest, I'm salivating to see it. No ccx compromise and expected improved foundry. Good laptop chips are kind of given now, seeing zen's core strength and weakness. Desktop chip quality will depend on how much GF can improve it's process, which should be good enough as they can already reach near 4GHz.

 

[mikk]

https://benchlife.info/amd-zen2-and-zen3-with-7nm-node-on-list-05172017/

Confirmation that Pinnacle Ridge must be Zen as we knew already from the leaked roadmap. Next Zen update will be on 7nm, but that won't happen next year.

 

[iBoMbY]

Well, as I told everyone weeks ago. Pinnacle Ridge will probably bring new features, and a lot of bug fixes, but not much (if anything) on the IPC front. What would be on my wishlist: PCIe 4.0, upgraded Memory Controller (higher supported standard, and higher supported OC ranges), upgraded Infinity Fabric (fewer latency problems), and hopefully higher stable clocks.

 

[jpiniero]

Well, it's possible that based upon that other slide about the servers that Pinnacle Ridge has 6 cores per CCX instead of 4.

 

[Gideon]

Well, as I told everyone weeks ago. Pinnacle Ridge will probably bring new features, and a lot of bug fixes, but not much (if anything) on the IPC front. What would be on my wishlist: PCIe 4.0, upgraded Memory Controller (higher supported standard, and higher supported OC ranges), upgraded Infinity Fabric (fewer latency problems), and hopefully higher stable clocks.

At least it will almost certainly be produced on 14nm+ process

 

[Topweasel]

PCIe 4.0 doesn't come till AMD is ready for AM5. They have said the 2 big things that will cause them to switch sockets is DDR5 and PCIe 4.0. Mainly because both would make the CPU unsupported on current boards.

 

[Abwx]

What is the definition of a "Tock" in AMD's parlance?

A uarch improvement wether there s a node shrink or not, if there s one there will be a uarch update in the same row, so translated in Intel terminology it means either a tock or a (tick + tock).

 

[whm1974]

PCIe 4.0 doesn't come till AMD is ready for AM5. They have said the 2 big things that will cause them to switch sockets is DDR5 and PCIe 4.0. Mainly because both would make the CPU unsupported on current boards.

That I doubt that the consumer market even the HEDT needs DDR5 and/or PCIe 4.0 yet.

 

[formulav8]

What is the definition of a "Tock"

uArch improvements are tocks usually. Not taking process size as the indicator which are ticks. IMO, its current zen, then another Zen uArch improvement still on 14nm but an improved 14nm process (Samsung's 14nm LPU). Then another uArch improvement on 7nm. But honestly, only AMD knows the true way to describe it.

 

[iBoMbY]

PCIe 4.0 doesn't come till AMD is ready for AM5. They have said the 2 big things that will cause them to switch sockets is DDR5 and PCIe 4.0. Mainly because both would make the CPU unsupported on current boards.

PCIe 4.0 is backwards compatible, and there should be no problem with the current AM4 boards and chipsets. And AMD is using the same chip in their Epyc server CPUs, and they would definitely profit from PCIe 4.0. DDR5 may be another matter.

 

[Atari2600]

PCIe 4.0 is backwards compatible, and there should be no problem with the current AM4 boards and chipsets.

Its not backwards compatible at both ends!!

i.e. you can stick a GPU that is PCIe3.0 into a PCIe4.0 slot and it'll work, but you cannot hook up a CPU capable of supporting up to PCIe3.0 into a PCIe4.0 motherboard and expect that to work.

 

[iBoMbY]

Of course you can, with lower performance, unless the chipset only supports PCIe 4.0, or newer CPUs. But that shouldn't be a problem at all. If you have an X370 PCIe 3.0 chipset with a PCIe 4.0 CPU, the CPU can downgrade the link to PCIe 3.0, and if you have a PCIe 4.0 chipset, and a PCIe 3.0 CPU, the chipset could downgrade to PCIe 3.0. I really don't see a problem either way, if it is done right.

 

[Atari2600]

I really don't see a problem either way, if it is done right.

For that, a CPU designed and built several years before the standardisation of PCIe4.0 has to recognise the handshake protocols and react accordingly.

While theoretically not impossible if the standards group have imposed protocols looking ahead several iterations, its extremely unlikely.

 

[otinane]

So Pinnacle Ridge (2018) will be 14nm+. That OK.

Could we expect RR desktop (we know that mobile RR will launch end 2017) launching 2018 will fall into Pinnacle Ridge batch, or it will be the same as the mobile version ?

 

[nathanddrews]

There are all manner of features that can be added or tweaked and improvements that can be made within the same process and architecture: they're called revisions (or stepping). No ticks or tocks required.

 

[iBoMbY]

For that, a CPU designed and built several years before the standardisation of PCIe4.0 has to recognise the handshake protocols and react accordingly.

While theoretically not impossible if the standards group have imposed protocols looking ahead several iterations, its extremely unlikely.

PCIe was designed with future versions in mind. The compatibility works in all ways possible. If I remember correctly, the connection is always initialized at the lowest (PCIe 1.0) protocol/link speed level, and the devices exchange their info on supported standards and extensions, and then the link speed is upgraded to the highest common denominator afterwards.

See also the FAQ:

PCI-SIG is proud of its long heritage of developing compatible architectures and its members have consistently produced compatible and interoperable products. In keeping with this tradition, the PCIe 3.0 architecture is fully compatible with prior generations of this technology, from software to clocking architecture to mechanical interfaces. That is to say PCIe 1.x and 2.x cards will seamlessly plug into PCIe 3.0-capable slots and operate at their highest performance levels. Similarly, all PCIe 3.0 cards will plug into PCIe 1.x- and PCIe 2.x-capable slots and operate at the highest performance levels supported by those configurations.

 

[Atari2600]

Your still talking about the peripheral side of things.

The CPU has to work together with the chipset to provide a PCIe4.0 platform. Both of them have to be aware of what the other can, and cannot offer.

If, for instance, supporting PCIe4.0 on the CPU requires additional pins, then AM4 physically cannot work. If it requires signal muxing - then the old AM4 CPU has to be able to understand any combined signalling.

Again - not physically impossible - but very unlikely.

Has there been any historical instance of motherboards, chipsets and CPUs supporting a yet to be released standard?

 

[iBoMbY]

Okay, you don't get it. I'm giving up.

 

[Topweasel]

Okay, you don't get it. I'm giving up.

No you don't get it. You are talking protocol and not actual hardware information. The pin out on the PCI-E has to be the same. The socket itself has to be the same. The handshake can happen at certain point. But actual CPU implementation and pin out and change possible processing can be not supported on the socket. The wasn't an issue with AM3 and AM2 because it had it's own front side bus and the PCI-e communication was handled by the chipset and not the CPU. PCIe's actual physical implementation can change, even if the consumer end connectors and standards don't.

Think USB 3. Sure all the USB 3 devices can speak to all USB controllers. They hand shake the thumbdrive runs at 2.0 and windows says it could be running faster if you plugged it into a 3.0 port. But that doesn't mean USB 3 controllers are the same as USB 2 controllers and that they use the drivers and communicate the same way. It's one way backwards compatibility the end device doesn't care if it's higher or lower version. As long as both find a common denominator. But that ignores all the back end works and basically assumes that all PCE 4.0 will be is AMD flipping a switch and saying run faster.

You know best way to describe it is device to device can be negotiated at the different protocols. By why would you assume that all of a sudden the actual bus assignment chip (the CPU) can change without changes to the bus itself?