This is the direct quote from the Software Optimization Guide for the AMD Zen5 Microarchitecture published in August 2024, revision 1.00:
So I took it to mean that the setup is asymmetrical, since they underline only the first slot, not any slot, of course I might have read into it too literally, but in that case I find the wording confusing. Still, it would be a waste to put more "complex" decoders in, if only the first slot will do the "complex" decoding, unless this is being muxed for some purpose.
Decode pipe0 = D0,D1,D2,D3So I took it to mean that the setup is asymmetrical, since they underline only the first slot, not any slot, of course I might have read into it too literally, but in that case I find the wording confusing. Still, it would be a waste to put more "complex" decoders in, if only the first slot will do the "complex" decoding, unless this is being muxed for some purpose.
Yeah, I was guessing here regarding the 2 micro-op queues in Zen 5His diagram contains errors (there is only one complex decoder in the cluster if we are to trust software optimization guide) so I would not rule out other mistakes.
So I took it to mean that the setup is asymmetrical, since they underline only the first slot, not any slot, of course I might have read into it too literally, but in that case I find the wording confusing. Still, it would be a waste to put more "complex" decoders in, if only the first slot will do the "complex" decoding, unless this is being muxed for some purpose.
Thanks for explanation. Obviously this was lack of knowledge on my side as I have simply assumed the split was done on the instruction length and not on the micro-ops produced.x86 considers instruction "simple" when it outputs just one micro-op. Complex instructions output at least 2 micro-ops. All AMD decoders sans K5 are "complex" - being able to decode instructions which output more than just one mop. Intel decoders are split to simple and complex - simple decoders can only decode one-to-one mapped instructions - meaning hardware instruction is equal to ISA instruction and does not split to multiple different instructions.
Looks plausible, given that the µop cache is dual-ported. (The split could be static or dynamic though...)I was guessing here regarding the 2 micro-op queues in Zen 5
To quote: https://chipsandcheese.com/p/amds-strix-point-zen-5-hits-mobile(a) how many µops/cycle a single thread can pull from the µop cache: up to 6, or up to 6+6?,
This also matches what can be found in software optimization guide (chapter 2.9.1)To further speed up instruction delivery, Zen 5 fills decoded micro-ops into a 6K entry, 16-way set associative micro-op cache. This micro-op cache can service two 6-wide fetches per cycle. Evidently both 6-wide fetch pipes can be used for a single thread.
The Op Cache (OC) is a cache of previously decoded instructions. When instructions are being
fetched from the Op Cache, normal instruction fetch and decode are bypassed. This improves
pipeline latency because the Op Cache pipeline is shorter than the traditional fetch and decode
pipeline. It improves bandwidth because the maximum throughput from the Op Cache is 12
instructions per cycle, whereas the maximum throughput from the traditional fetch and decode
pipeline is 4 instructions per cycle per thread.
Too bad Zen6 deprecates itSomebody found a nice use (huge performance boosts?) for the VP2INTERSECT instruction in Zen 5.
Using the most unhinged AVX-512 instruction to make the fastest phrase search algo
Disclaimers before we start For those who don’t want to read/don’t care that much, here are the results. I hope after seeing them you are compelled to read. TL;DR: I wrote a super fast phrase search algorithm using AVX-512 and achieved wins up to 1600x the performance of Meilisearch. The source...gab-menezes.github.io
It seems great, until you realize this particular release targets a product released in Oct 2024. That means this release is a 3 months late...Very impressive gains, 2025 I think will finally showcase the software reorg AMD has been working on for some years.
What kind of logic is that? Does that mean every ray traced game coming out this year is 5yrs late? Software is done when it's done. And 3mo "late" it's better than never at all, like AMDs previous form. 400% is worth the delay. I take it this will run even better on MI300...It seems great, until you realize this particular release targets a product released in Oct 2024. That means this release is a 3 months late...
Wrong. Turin servers were not "released" in October 2024.this particular release targets a product released in Oct 2024.
Progress is progress.It seems great, until you realize this particular release targets a product released in Oct 2024. That means this release is a 3 months late...
I find this comparison lacking in details. I mean they give you enough to be able to compare ZenDNN against ZenDNN, but not against other solutions. You don't know if they are playing catch-up, or they actually improved things. I mean inference is heavily dependant on memory BW, they don't give information on what that memory BW is, so it is hard to estimate how it would do against other frameworks.Very impressive gains, 2025 I think will finally showcase the software reorg AMD has been working on for some years.
They compare it to IPEX 2.4.0 iso-hardware.I find this comparison lacking in details. I mean they give you enough to be able to compare ZenDNN against ZenDNN, but not against other solutions. You don't know if they are playing catch-up, or they actually improved things. I mean inference is heavily dependant on memory BW, they don't give information on what that memory BW is, so it is hard to estimate how it would do against other frameworks.