Maybe. But more ports is actually the expensive part.
The obvious low hanging fruit for future cores is to fix the regression caused by a hazard that seemed unintentional and unrelated to width of the instruction.
Maybe. But more ports is actually the expensive part.And yet a rather obvious low hanging fruit for future cores to improve upon.
It's less a server cache scheme than it's dictated by the overall core architecture. x64 targets high clocks so they have more levels of cache to ensure the closest one are fast. So what we might get are even more levels [Lion Cove with L0] or slight size increases unless they will pivot and go for wider and slower cores.Fascinating...
One thing I read somewhere is that Apple's performance success comes also from a fairly fat L2 rather than the more server-typical L1/2/3 AMD uses.
Now granted they also do it in GPUs while Nvidia stays with only L1/L2, maybe it's just a kink AMD will keep. But could it be that with Zen 6, we start seeing the latency bottleneck cured with a smaller or non-existent L3 on client, while a really fat L2 replacing it? Server apps very clearly gain a lot from Zen 5, the problem seems to be more that what we have here is a fully primed server chip that isn't really any kind of improvement in client.
At the moment P-cores have already 3 load ports for fp, are they doing considerably better than Zen4?Not the point. AMD does have only 2-load ports to fp register where everybody else has more. Even Intel E-cores will have 3 load ports, so probably being able to achieve better IPC for some scalar & 128 bit workloads. AMD has biggest FP-unit of all in their cpu's - and is nearly in situation that it will have worst IPC for desktop and mobile workloads.
Once again it depends on the workload. Alex has shown that this is the case for Y-cruncher SSE kernels, but Geekerwan has shown that for SSE SPECfp, there is a net improvement, so it depends It's important to note that most basic operations [add/substract/multiply/fma] had already 3 cycle latency for FP, so they are not affected by the latency increase. It's not like everything is worse, and people treat it as general regression...http://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/ Ever so slightly, a percent or two.
It really depends on the code. If we look at Spec as generalized proxy of "real" FP workload, then Zen4 was doing pretty fine vs Intel and Zen5 [both Strix and Granite] improved considerably with or without AVX512.Theoretically most powerful - but in real usage cases might actually be worst performer. That's a pretty imbalanced situation.
Seems unlikely to not say almost impossible for Zen 6...and even for 7 AMD is still probably going to follow up on their penny pinching philosophy.It's less a server cache scheme than it's dictated by the overall core architecture. x64 targets high clocks so they have more levels of cache to ensure the closest one are fast. So what we might get are even more levels [Lion Cove with L0] or slight size increases unless they will pivot and go for wider and slower cores.
Even if it were treated as a total regression, it's 1%. AVX 512 bit ops have a literal 99% upgrade with minimal latency. If anything, Zen 5 may surprisingly FineWine. We may see a great effort in compilers to massively improve AVX 512 usage in future programs.Once again it depends on the workload. Alex has shown that this is the case for Y-cruncher SSE kernels, but Geekerwan has shown that for SSE SPECfp, there is a net improvement, so it depends It's important to note that most basic operations [add/substract/multiply/fma] had already 3 cycle latency for FP, so they are not affected by the latency increase. It's not like everything is worse, and people treat it as general regression...
So from the currently available performance counters it seems the main culprit of Zen 4 IPC is the frontend - L1I misses are horribly up and L2BTB overrides are... wtf. This means either the counters are broken or the frontend lags behind Zen 4.https://blog.hjc.im/zen-5-more-details-2.html 2nd part of David Huang's Strix Point analysis
C&C confirms that Zen 5 can't decode >4 instructions when running a single thread. This means the clustered decoder is way less 1T-capable than 2020 Tremont...C&C Zen 5 and Zen5c article.
The increase in L1i misses in gcc and perlbench makes no sense. If it really was that bad the score would have been significantly lower, not better.So from the currently available performance counters it seems the main culprit of Zen 4 IPC is the frontend - L1I misses are horribly up and L2BTB overrides are... wtf. This means either the counters are broken or the frontend lags behind Zen 4.
How much smaller? Than which Zen 5C? There are at least two Zen 5C.Skymont is much smaller than zen 5c.
If that was the case then Zen 5 wouldnt have 9-13% better ST IPC than RPL, so there s rather something broken in the measuring methodology than in the decoder capabilities.C&C confirms that Zen 5 can't decode >4 instructions when running a single thread. This means the clustered decoder is way less 1T-capable than 2020 Tremont...
Skymont is about 30% area of lioncoreHow much smaller? Than which Zen 5C? There are at least two Zen 5C.
And does that mean anything without a comparison of area of Lion Core to Zen 5?Skymont is about 30% area of lioncore
Zen 5c is about 75% area of Zen 5
Zen 5c is about 75% area of Zen 5, on stx(tsmc n4)And does that mean anything without a comparison of area of Lion Core to Zen 5?
N3 Zen 5C hasn't been measured yet, as far as I'm aware. I remain curious how you were able to state it so confidently.
There was this:And does that mean anything without a comparison of area of Lion Core to Zen 5?
N3 Zen 5C hasn't been measured yet, as far as I'm aware. I remain curious how you were able to state it so confidently.
It's also that if it was indeed front-end that was the problem, we would see degradation in branchy workloads like web browsing, no? But that does not seem to be the case.The increase in L1i misses in gcc and perlbench makes no sense. If it really was that bad the score would have been significantly lower, not better.
I can think of two hypotheses (warning, I'm at my first coffee...): they changed the way they count Icache misses, or the second group of decoders (which doesn't seem to work as many expected) is counting misses while doing nothing or being bugged.
And N3E Zen 5C vs N3B Skymont?Zen 5c is about 75% area of Zen 5, on stx(tsmc n4)
If that was the case then Zen 5 wouldnt have 9-13% better ST IPC than RPL, so there s rather something broken in the measuring methodology than in the decoder capabilities.
xz leela and deepsjeng have difficult to predict branches (string comparisons, evaluation functions in game trees) and they don't have improvements or even slight regressions.It's also that if it was indeed front-end that was the problem, we would see degradation in branchy workloads like web browsing, no? But that does not seem to be the case.
The uops cache doesnt generate uops out of the vaccum, it still rely on the decoders decoded instructions flow to build its uops tables, if the decoding bandwith is not increased in respect of Zen 4 then uop cache related instructions flow wont increase and IPC will be stagnant.The µop cache can serve more ops per cycle to single thread.
The uops cache doesnt generate uops out of the vaccum, it still rely on the decoders decoded instructions flow to build its uops tables, if the decoding bandwith is not increased in respect of Zen 4 then uop cache related instructions flow wont increase and IPC will be stagnant.
How much cycles before the decoder is put to use.?.You got it wrong. When uop cache hits it will reuse already decoded instructions and decoders aren't needed at all. Actually cpus will shut down decoders completely when loops are 100% cached in uop cache. Decoders are only needed when uop cache won't hit, and when they hit even partiallly CPU IPC can grow above decoding capabilities.