Discussion Zen 5 Builders thread

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PJVol

Senior member
May 25, 2020
696
618
136
It also says 1T, but only running 2000 FLCK
FCLK is fully decoupled from UMC/DDR Phy clock domains, though at the cost of BW due to FIFO losses.
The desired FCLK is a trade-off between these losses and the Data Fabric throughput.

And, as has always been the case with MCM Zen memory subsystem, a question of prioriy: latency or bandwidth.

As for the memory speed, there's a MCLK threshold after which the UMC operates at a 1:2 ratio. I believe 3600 is well above that, though Zen4 owners may correct me.
 
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Reactions: Josh128

Hotrod2go

Senior member
Nov 17, 2021
349
232
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My 9700X with 2167 FCLK needs 0.095 less volts to run stable compared to my 7600X with the same FCLK speed in the same motherboard. The MemTestPro test for over 700% coverage in my system with an X670E board & EXPO 5600MT/S ram profile. I tweaked only the tREFI & both SCL's minor timings for that ram profile, but in the greater scheme of things, that's just a minor tweak to the ram itself. The surprising thing I found is the low SOC volts now needed, even with LLC of 3 for SOC which is the lowest LLC my board can do for that bios option.

So consequently, my 9700x runs significantly cooler than before thanks to the SOC not needing as much volts to be stable at 2167 FCLK & all this is with first iteration of AGESA code for Zen 5. Also much easier to sustain 5500MHZ PBO boost on all 8 cores with SMT enabled (auto settings for PBO) continuously during this test with MTP.
(note the slower last thread in MTP is because of Windows 11 23H2 scheduling issues)

To get perspective on some environmental factors influencing temps in this screenshot:
1. Antec C8 case, closed up.
2. Case fan profile on silent except cpu on standard.
3. Deep Cool AK620 tower cooler + Thermal Grizzley Kyronaut extreme TIM
4. RX 7900 RTX idling below the CPU
5. Windows power profile on high performance.

 

B-Riz

Golden Member
Feb 15, 2011
1,591
754
136
Need some feedback from the forum; I want to do fixed clock testing, starting with Zen5, then work down to Zen4, Zen3, Zen2 and Zen1.

I have a 7600X, no pure 6 core Zen3, a 3600, but no 6 core Zen1.

Would we be happy if I turned off half the 5900X (or limit a 5800X to 6 cores?) and limited the R7 1700 to 6 cores?

I am thinking the clock would have to be around 3.6 Ghz, I don't think the 1700 can do much more than that without too much voltage; I may look for a late production OG R5 1600 non AF.

Fastest GPU is a 7900 XT, then a 3090, then 3080 Ti.

Thoughts / suggestions?

This will take time to work through though. (could take a month or more of here and there testing)
 

Det0x

Golden Member
Sep 11, 2014
1,212
3,770
136
Seems like a slow Tuesday, so i guess i can share some binning results for my 3x 9950X retail + 1x 9950X ES, now that i have sold all my Zen5 cpus i wont daily (lost ~200$ per cpu on the used-market)

A few words before we get into the data:
  • The goal was to complete 3x MT runs in a row in Cinebench R23
  • Static cpu voltage was set at 1.200 vcore --> around 1.156 vcore get while running (since set in windows only hwinfo motherboard vcore is correct reading)
  • Static clockspeeds was upped on each individual CCDs in 25mhz intervals before it could not pass 3x runs back to back
  • I tried to keep the watercooled same loop GPU idle temp as close to 20 degrees as possible for all runs (most reliable for me)
  • Non of the runs were done at stock 5600MT/s speeds, but not maxed out either --> was just what i was running at the time of testing
  • Nevermind the R23 MT score themself as i had lots of stuff running, lowering the scores. Point of interest was clockspeeds
  • HWinfo got reset before each run, all runs seems to be about 256w powerusage while running Cinebench R23 MT
  • Stupid windows11 printscreen would only take screenshot the same millisecond the benchmark ended on all but the ES, but values in hwinfo hadn't had time to update
Retail #1 9950X sample
Max stable FCLK = 2167mhz
Max static R23 ST clockspeed @ set 1.4core = 5825mhz
Max completed MT clockspeeds = 5500mhz CCD0 / 5450mhz CCD1


Retail #2 9950X sample
Max stable FCLK = 2200mhz
Max static R23 ST clockspeed @ set 1.4core = 5850mhz
Max completed MT clockspeeds = 5550mhz CCD0 / 5425mhz CCD1


Retail #3 9950X sample
Max stable FCLK = 2200mhz
Max static R23 ST clockspeed @ set 1.4core = 5850mhz
Max completed MT clockspeeds = 5500mhz CCD0 / 5425mhz CCD1


ES 9950X delidded sample
Max stable FCLK = 2200mhz
Max static R23 ST clockspeed @ set 1.4core = 5900mhz
Max completed MT clockspeeds = 5475mhz CCD0 / 5525mhz CCD1


I have binning data for all samples at 1.100 vcore set also, but it pretty much shows the same as with 1.200 vcore set
 

Det0x

Golden Member
Sep 11, 2014
1,212
3,770
136
You wouldn't have lost any money if you had stamped their IHS "Det0x tested, tortured and still alive"
I dont want to have to deal with all the questions from selling a "binned" sample
Take the loss and move on.. have learned from selling Zen4 golden samples cpus

Some scrub with a 100$ motherboard + boxed CPU cooler and some micron memory is wondering why the cant copy my settings 1-to-1 and be rank1 on hwbot, and pretty much accusing me of "scamming him, nevermind he have no idea about anything 🤣
 

Hail The Brain Slug

Diamond Member
Oct 10, 2005
3,475
2,397
136
I dont want to have to deal with all the questions from selling a "binned" sample
Take the loss and move on.. have learned from selling Zen4 golden samples cpus

Some scrub with a 100$ motherboard + boxed CPU cooler and some micron memory is wondering why the cant copy my settings 1-to-1 and be rank1 on hwbot, and pretty much accusing me of "scamming him, nevermind he have no idea about anything 🤣
Damn if I knew you were going to sell the "bad" samples for $450 I might have bought one instantly. Especially #2 or #3
 
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