Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[A///]

I don't think they would do what Intel did. Charging $1000 for their useless Extreme Editions.

your memory must suck because amd was charging more than intel back in the p4 days for their ultimate processors.

 

[A///]

Not everyone needs a 8950X. Let's talk about the 8800X3D. I don't think it will go above $500.

we should be advocating amd to convince people to get the 8950x like opra.

 

[A///]

ignore the taco bit and pretend it says 8950x

 

[adroc_thurston]

You'd also create additional thermal interfaces in the thermal removal path that would probably increase cooling effort.

Nah, hybrid bonded parts are all pretty thermally efficient.
Just low ROI for additional cache stacks.

 

[A///]

Nah, hybrid bonded parts are all pretty thermally efficient.
Just low ROI for additional cache stacks.

what do you know about the ihs in on zen 5, temps, ram speeds possible...

adrock is secretly mike clark.

 

[Hitman928]

Nah, hybrid bonded parts are all pretty thermally efficient.
Just low ROI for additional cache stacks.

The interface between metals due to the bonding is very good (i.e., practically continuous) as long as the alignment is good. I'm not as sure about the interface between the silicon as you need an insulator between the TSVs to fill the gaps. I don't think it's bad, but if you start putting multiple of them, you get a thermal resistance ladder going. I don't have numbers or anything quantitative to go off of, but the layers will definitely introduce an additional resistance from the non-continuous structure and added thermal resistance of the insulator. I would expect this to have at least a measurable effect if doing it multiple times for a single design. If someone has info showing that resistance is negligible even in a design with high thermal density, then I'll be happy to be corrected here.

 

[PJVol]

here the pic you linked

Nothing is wrong with that pic, since I posted it along with two others just for illustrative purposes as an example of LDO VR, and the context of that post didn't imply any particular implementation thereof.
So this complaint is "Not accepted" (in a hope you've got something more substantial to back up your "clueless").

PS: regarding the scheme itself - it's analogue LDO btw, and if you really design ICs, then you wouldn't call error amplifier a comparator. This alone raises doubts about that, Dear IC designer ))

 

[Joe NYC]

Already does, Zen4 V$ overlaps L2 where power delivery TSVs now lie.

Requires rather invasive CCD redesign so not for Zen5.

AMD is already doing it for Mi300/400, but it would need a base die, which is most likely not happening for Zen 5

Minor ROI for a pretty high cost addr.
No bueno.
I know you want more but AMD will sell you the least amount they can get away with for maximum money.

I don't think AMD is as short- sighted as that.

AMD has a technology development cooperation with TSMC regarding advanced packaging and in particular SoIC, where AMD helps bring it to mass production.

The next logical step is to build multiple level high stacks of SRAM / V-Cache. I think AMD is going to go full steam on that with TSMC. It would not surprise me if Zen 4/5 are already designed to work with multiple levels of V-Cache.

So as far as AMD and TSMC working together, it is a 2 way street. At the end of it, TSMC wants to sell a lot of wafers, including a lot of N6 wafers and a lot of packaging services.

As far as return on investment into V-Cache, AMD is already selling it for $50 to $100, with extremely high margin. So, a multiple levels of V-Cache (2 or 4), AMD could add another $50 - $100 to MSRP.

 

[Joe NYC]

• - to cover greater area on top
  • You would then start to cover the logic circuity with active circuits, this would exacerbate the hotspot/thermal issues.

It does not mean this is an unsolvable problem. It seems that some way could be devised to put some "heat TSVs" through the cache die to channel the heat to the top of the chip. Or some other solution...

• - place it under the whole die
  • Do you mean swap the die stack order (i.e., put the V-cache die on bottom and the core die on top)? If so, that's not going to happen, all the input/output/gnd/power signals go out the bottom of the core die.

AMD is already doing all of this in Mi300, using the base die. So, it is a problem that is already solved. But at cost that is beyond what is affordable in client space at this time.

• - stack more layers, not just one - which apparently was the original plan for V-Cache
  • I don't think there are many niches left where even more L3 will help enough to be worth the cost. You'd also create additional thermal interfaces in the thermal removal path that would probably increase cooling effort.

People already spend money on useless cores (beyond, say 8). On useless e-cores. They deliver next to nothing to typical desktop / laptop users. Except in some niches. So let's not draw a line that has already been crossed.

V-Cache brings good benefits to gaming - which is not really a niche. It's for most people the only area where their computer is stretched to the limit. And the only reason why many people even consider upgrading their PC, if the PC is not broken.

If you look at the MindFactory bestsellers, the most knowledgeable buyers already opt (by a big margin) for spending extra money on V-Cache rather than more cores.

 

[adroc_thurston]

AMD is already doing it for Mi300/400, but it would need a base die

Atta boy.
MI300/400 MALL is no extended CPU L3, it's a memory side cache striped across IMCs.
A lot less wires involved.

 

[Joe NYC]

Atta boy.
MI300/400 MALL is no extended CPU L3, it's a memory side cache striped across IMCs.
A lot less wires involved.

The die is already cast for Zen 3/4/5? that the TSVs for V-Cache have to go up to the top of the die, and it cannot be changed. So probably a waste of time to speculate otherwise.

But more layers on top - that is feasible, and like I said, possibly already part of the Zen 3/4/5 design. Just a question of when it is manufacturable by TSMC and bringing the costs in line.

With Wafer on Wafer stacking, the costs per die should become quite low. It's like > 1,500 dies per wafer bonded in one step.

 

[adroc_thurston]

possibly already part of the Zen 3/4/5 design.

Yea Breckenridge was tested with up to 4-hi configs.
Only 1-hi made it out since ROI for anything bigger is not there.

 

[Abwx]

Nothing is wrong with that pic, since I posted it along with two others just for illustrative purposes as an example of LDO VR, and the context of that post didn't imply any particular implementation thereof.
So this complaint is "Not accepted" (in a hope you've got something more substantial to back up your "clueless").

PS: regarding the scheme itself - it's analogue LDO btw, and if you really design ICs, then you wouldn't call error amplifier a comparator. This alone raises doubts about that, Dear IC designer ))

Lol, playing with words without knowing their meaning, the wording i use is right, this is a comparator, that s the right terminology wich is generic because it s a circuit that compare two or more values, there s not only error amplifiers used as comparators, in PLLs that generate frequencies using a quartz as reference an EXOR gate is often used as comparator...

Comparator - Wikipedia

en.wikipedia.org

As i said, do your homework, you just embarassed yourself yet another time...

Edit : Think a little rather than trying to contradict with hollow thoughts.

It s much more efficient to switch a mosfet at full conduction during short periods rather than to keep it partialy conducting all the time.

In the first case the voltage drop across the mosfet is very low even if the current is high because it is fully saturated, in the second case the fet conduct partialy and the voltage drop is much higher, hence losses are also much higher despite a lower current.

I could do a basic math demonstration but i hope that those explanations are enough.

 

[naukkis]

Mosfets can have very low resistance, voltage drop will be negligible, and think putting 10 000 or more in parallel, in a CPU such a quantity is free, beside they are connected as common source, just like the rest of the CPU circuitries, that s the only mode that make sense in digital circuitry, you ll never see common drain connected mosfets since that would require a second voltage rail ( and even a third to drive the Pfets) to drive them efficently to get the lower possible RDSon (RDSON = Drain-Source Resistance when the device is switched on)

In Zen since that s the positive rail that is power switched it s Pfets that are used as switches, by principle they have higher RDSon than Nfets and are the frequency limiting devices in CPUs much more than Nfets, but as said since they can be paralleled at will that s not a big issue.

Driving tens of thousands of mosfets at high frequencies is anything but free. AMD:'s integral voltage regulation main target is to fine tune cpu core power - mainly to give priority core a bit more voltage than the rest of cores so voltage drop in that circuit is usually something like 10%. With just 10% voltage drop switching power supply is much more inefficient that linear regulation. And for voltage rails - in cpu there is many voltage rails. That integral regulation makes additional voltage rails from cpu's prime rails - and supply voltage to that regulation can be easily fed from SOC-voltage rail which makes it way easier to implement as regulation power supply is always stable. That's why there's is that SOC voltage rail - to provide stable voltage to parts of cpus where needed. For efficiency it's obvious that common drain fets are used.

 

[naukkis]

In the case of a purely non switching linear regulators losses are high because the mosfet Mp is forcibly used in its linear region and has a high resistance, while if switched it is used in its saturation region, meaning that it has minimal resistance compared to the previous case, to limit and set the output voltage to the desired value the duty rate of the square signal will be modulated accordingly by the comparator.

Mosfets aren't used in linear region. Read that AMD patent papers, there is many of linear regulators in paraller so logic can activate varying numbers of them on on off to change resistance. Actual resistance is probably achieved with wiring not the fets making thermal manageement much easier.

 

[yuri69]

They'll charge $999 for 8950X instead.
lack of comp isn't good either way.

Given Zen 6 is not expected before H2 2026, Zen 5 somehow has to compete with multiple Intel generations. 2024 is Meteor/Arrow. 2025 for Lunar? 2026 for Panther? Zen 5 has to stay relevant vs all those competitors until Zen 6.

 

[adroc_thurston]

Given Zen 6 is not expected before H2 2026

Who said that even.

2024 is Meteor/Arrow

Garbage.

2025 for Lunar?

I don't think 10W SoCs are relevant and neither does AMD.

2026 for Panther?

Seems minor outside of Atom spam (and that's not where Intel's issue lies).

 

[exquisitechar]

Given Zen 6 is not expected before H2 2026, Zen 5 somehow has to compete with multiple Intel generations. 2024 is Meteor/Arrow. 2025 for Lunar? 2026 for Panther? Zen 5 has to stay relevant vs all those competitors until Zen 6.

Why would it be H2 2026? That would make for an unusually long wait between Zen 5 and 6. Competing with Arrow Lake doesn't seem to be a tall order based on Intel's own projections and Panther should mostly compete with Zen 6.

 

[Thibsie]

In a way I am sad that Zen 5 appears to be such a leap over Zen 4, and is coming soon. I just finished spending about $15,000 on 3 Genoa systems. Now they will be blown out of the water by Zen 5 !

Gimme, gimme xD

 

[Abwx]

Mosfets aren't used in linear region. Read that AMD patent papers, there is many of linear regulators in paraller so logic can activate varying numbers of them on on off to change resistance. Actual resistance is probably achieved with wiring not the fets making thermal manageement much easier.

I was talking of a classical LDO, even if the mosfet is connected as common source it will still be used in its linear region, common drain is not possible with a single voltage rail for the reason i state below.

For efficiency it's obvious that common drain fets are used.

I beg to differ, common drain is not possible because it require to set the gate voltage higher (or lower with a Pfet) than what is possible with a single power rail to have full conduction of the device, so for efficiency common source is the norm.

Beside, and it s not adressed to you specially, someone posted this pic :

And it stated at wikichip :

In Zen, each core has a digital LDO regulator

In the pic above two banks of Pfets are used to control the voltage, these are forcibly connected as common source, beside they are digitaly driven, wich means that it s the duty rate of a square signal that set the conduction time and hence the voltage.

It can be also called digital if the Pfets are driven by a digital to analog converter (DAC), but a high precision DAC is not easy to implement at such low voltages and it s way more easy to use a pulse width modulation (PWM) to control the fets conduction, the voltage at the output of the fets is then filtered (integrated mathematically speaking) by capacitors.

 

[naukkis]

I beg to differ, common drain is not possible because it require to set the gate voltage higher (or lower with a Pfet) than what is possible with a single power rail to have full conduction of the device, so for efficiency common source is the norm.

In case with Ryzen processors -source isn't fixed voltage but varies, main rail voltage is fixed to highest core voltage. If I was a designer of such a system targeting high efficiency I sure would take driving currents from stable source - and as efficiency is target common drain is better option than wasting driving current. Ic designers aren't stupid - sure they would target to highest possible efficiency.

 

[Abwx]

In case with Ryzen processors -source isn't fixed voltage but varies, main rail voltage is fixed to highest core voltage. If I was a designer of such a system targeting high efficiency I sure would take driving currents from stable source - and as efficiency is target common drain is better option than wasting driving current. Ic designers aren't stupid - sure they would target to highest possible efficiency.

If you implement a common drain Nfet in serial with the positive rail then you need a voltage that is higher than the drain voltage (so higher than the positive rail) to drive the Nfet gate and get it in full conduction if it s required, thats a basic of fets behaviour, you must have the gate voltage at (drain voltage + Vth), Vth being the gate voltage threshold of the fet.

Common drain is not possible as i said, it s explicitely common source on the pic above since these are Pfets that are in serial with the positive rail, their gate can be brought at a way lower voltage than their drain, wich allow full conduction when the core is at max frequency and require the highest possible supply voltage.

 

[APU_Fusion]

I am close to ordering new 7950x3d+4090 system. are we looking at Q1 release for Zen5? I am tired of waiting but don‘t want to spend money on old processor if it will be placed soonish.

 

[igor_kavinski]

I am tired of waiting but don‘t want to spend money on old processor if it will be placed soonish.

You are late to the party. Better hold off. You might be able to snag a Zen 5 with 4090 Ti for the same money. If I had spent my money wisely and had just waited, I would be sporting a 7800X3D with a 7900 XTX instead of a 12700K with 3090.

 

[A///]

h2 2026... lol sure and half of us can sprout wings and fly.