LinkedIn leaks pointed to Zen6 being 3nm and Zen6C being 2nm. Plus a fancy packaging tech is repeatedly mentioned.Who said that even.
Pretty sure it was Zen5 being 3nm and Zen6 being 2nm. Oh well.LinkedIn leaks pointed to Zen6 being 3nm and Zen6C being 2nm. Plus a fancy packaging tech is repeatedly mentioned.
So the manufacturing has to be up and way cheaper than Apple accepts by the time Zen 6 can be readied.
| Cycle1 | Cycle2 | Cycle3 | Cycle4 | Cycle5 |
| RegRead (512-bit) | MUL (256-bit)(P0) | B. ADD (256-bit)(P2) | RegWriteB (256-bit) | |
| MUL (256-bit)(P0) | B. ADD (256-bit)(P2) | RegWriteB (256-bit) |
Given Zen 6 is not expected before H2 2026, Zen 5 somehow has to compete with multiple Intel generations. 2024 is Meteor/Arrow. 2025 for Lunar? 2026 for Panther? Zen 5 has to stay relevant vs all those competitors until Zen 6.
Yea that's all available by late'25.LinkedIn leaks pointed to Zen6 being 3nm and Zen6C being 2nm
Apple is of no relevance anymore with smartphone market being on its last breath.So the manufacturing has to be up and way cheaper than Apple accepts by the time Zen 6 can be readied
What's replacing the smartphone?Apple is of no relevance anymore with smartphone market being on its last breath.
Big boy real computing.What's replacing the smartphone?
intel will be lucky if they can launch Arrow Lake in Q4 2024. That means the next desktop big core launch is at least 1 year away, meaning late 2025.Seems that your assumption is that Intel design teams are 4x better / faster than AMD design teams, in being able to release 4 designs in time it takes it take AMD to release 1.
Maybe Pat can adopt it, next to "5 nodes in 4 years":
4 designs in time of 1 design of the competition
You may use whatever wording you want, but the thing is you can use opamp as comparator, but not vice versa.the wording i use is right, this is a comparator, that s the right terminology wich is generic because it s a circuit that compare two or more values,
If he could not, i gladly dispose him of one of those Genoa systems.... for a small fee :-DI'm sure you can squeeze at least ONE 8950X into your house
I gathered from this thread that the step up in single-threaded performance will be larger than the step up in all-core power-limited workload performance. (The latter kind of workloads, also known as embarrassingly parallel workloads, is what you are using your high core count computers for most of the time, AFAIK.) — If this thread wasn't bloated with so much off-topic talk, I would browse back to look for all-core performance projections…In a way I am sad that Zen 5 appears to be such a leap over Zen 4, and is coming soon. I just finished spending about $15,000 on 3 Genoa systems. Now they will be blown out of the water by Zen 5 !
Agree that if it s an OPAMP it s an error amplifier, but in this case the opamp is often use as straight comparator with or without gain, the DC Vref will be applied to one of its input and it yield a purely analog linear regulatorYou may use whatever wording you want, but the thing is you can use opamp as comparator, but not vice versa.
And again, the pic was for demonstrative purpose only. Of course the real LDO imply the use of negative feedback to the amplifier.
You're revealing your age there old timer with that abba reference.Gimme, gimme xD
???????Big boy real computing.
Just look at TSM revenue split past Q.
Between Zen 3 and Zen 4 launches Intel competed with core IP designs: Comet Lake, Ice Lake, Tiger Lake, Rocket Lake, Alder Lake & Gracemont. During the Zen 3-Zen 4 period Intel fielded Tiger Lake, Rocket Lake, Alder Lake, and missed Raptor Lake by a month.Seems that your assumption is that Intel design teams are 4x better / faster than AMD design teams, in being able to release 4 designs in time it takes it take AMD to release 1.
Maybe Pat can adopt it, next to "5 nodes in 4 years":
4 designs in time of 1 design of the competition
Sure, late '25 for volume of 2nm at TSMC but not AMD. AMD doesn't seem to have the tendency jump the node immediately, right?Yea that's all available by late'25.
Apple is of no relevance anymore with smartphone market being on its last breath.
Zen6 isn't N2.Sure, late '25 for volume of 2nm at TSMC but not AMD
They do whatever fits the bill the best.AMD doesn't seem to have the tendency jump the node immediately, right?
I'll go with cheaper and proven process for amd. no point in spending apple wafer money for n2 especially with 2 very new technologies being used. no doubt tsmc can pull it off but there's always that if that creeps back in one's skull.They do whatever fits the bill the best.
Works for mainstream.I'll go with cheaper and proven process for amd
N2 is just GAAs, and dense CCD for Zen6 is N2, yea.no point in spending apple wafer money for n2 especially with 2 very new technologies being used.
what about the back side power thing? am I mixing them up with samsung for 2nm or did tsmc prop the power delivery for something like n2e if it exists?Works for mainstream.
N2 is just GAAs, and dense CCD for Zen6 is N2, yea.
That's N2p only, which is like late'26 ramp.what about the back side power thing?
which is why the other one yuri said what he said, he was referring to that lte 2026 ramp for amd. although anyone who has not been sleeping will know that amd gen to generation release schedule was far less than 24 months and only remember the covid release period. even zen 3 was allegedly late for a nearly 17 or 18 month period. zen 2 was almost 24 months. you clearly know something we don't or work for amd yourself because you didn't bother correcting me when i mentioned ces or early q2 the last few days.That's N2p only, which is like late'26 ramp.
Vanilla Zen6 isn't N2.he was referring to that lte 2026 ramp for amd.
Vanilla Zen6 isn't N2.
They will, for Dense.other than having absurdist ideas amd would want to pay full price on a node that apple