Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Joe NYC

Platinum Member
Jun 26, 2021
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They published Zen 4 expected IPC uplift 6 months before launch, granted they did unveil only 60% of the real number but if Zen 5 is to be lanched in mid 2024 they should give some hints, beside shareholders and other investors want some numbers, so eventually they ll talk about it when they ll release Q4 2023 earnings.
Or, they may concentrate on Strix laptop chips at CES and have a separate event for Zen 5 server and desktop announcement.
 

Ajay

Lifer
Jan 8, 2001
16,094
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As I see, finally people are starting to see the light that desktop is a nieche market, and what happens on this market does not define anything.

Mobile is more important market.
A lot of units are sold, but nowadays they’re almost all cheapo SFF units for 10s of millions desk droids in offices. Intel dominates with equally cheap CPUs. Tiny margins. As the man above said not worth it for AMD to pay to play for almost nothing in return.
 

biostud

Lifer
Feb 27, 2003
18,402
4,966
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As I see, finally people are starting to see the light that desktop is a nieche market, and what happens on this market does not define anything.

Mobile is more important market.
Well since AMD is using the same CCX for desktop, laptops servers and HEDT it is all pretty much connected.
While I don't know exactly how much a role it plays, I think brand recognition is also a factor. I think AMD would very much like to change the "nobody has ever been fired for choosing Intel", and if AMD can show they are the top dog in all x86 markets then they will get there faster.
 
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JoeRambo

Golden Member
Jun 13, 2013
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If you people watched cpu Jesus tour of amd labs you will know why we won't see consumer dual ccd with 3d cache on both ccds.

Hint cache coherence between ccds...

Anything more specific on this claim? Video, time?
I have skipped over the videos, maybe missing the one specific ones.

Still "cache coherence" argument seems rather weak to me. L3 is victim cache, not quite sure why suddenly coherence network, broadcast and snoop traffic would breakdown from additional 64MB of L3? I think by definition L3 controller is already handling snoops for 32MB, and "content" came from evictions that already "passed" the network in first place.
 
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itsmydamnation

Platinum Member
Feb 6, 2011
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Anything more specific on this claim? Video, time?
I have skipped over the videos, maybe missing the one specific ones.

Still "cache coherence" argument seems rather weak to me. L3 is victim cache, not quite sure why suddenly coherence network, broadcast and snoop traffic would breakdown from additional 64MB of L3? I think by definition L3 controller is already handling snoops for 32MB, and "content" came from evictions that already "passed" the network in first place.

Being specific , they said when they tested dual CCD vcache in games , it didnt give performance advantage when threads get scheduled across both CCD's for obvious reasons , so they didn't productise it. having a higher core / cost part with 0 performance improvement for its target market isn't ideal.
 

soresu

Platinum Member
Dec 19, 2014
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Being specific , they said when they tested dual CCD vcache in games , it didnt give performance advantage when threads get scheduled across both CCD's for obvious reasons , so they didn't productise it. having a higher core / cost part with 0 performance improvement for its target market isn't ideal.
Makes sense.

Until games (realistically game engines now) start requiring >8 threads at minimum for basic performance levels that will probably remain the case.
 
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Bigos

Member
Jun 2, 2019
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Mobile is using different a CCX, unless you are talking about 7x45 parts which are desktop Raphael in disguise. At the very least, a mobile CCX - in Phoenix - has less L3 cache, other changes are possible (though I don't think they were ever discovered). And TSMC N5 vs N4 are similar but not the same process node requiring a different implementation (at least the last steps, the RTL is probably common). There is also Phoenix 2 which is completely different.

And regarding using the same CCD on both server and desktop, that is making the same design have to work on two completely different clock ranges. This facilitates products such as Threadripper that have high frequency with high amount of cores, but that is niche. AMD would be better off optimizing for low-ish frequency for data center and high frequency for desktop and mobile, and it appears from rumors this is what Zen6 will bring.
 
Jul 27, 2020
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Could Intel be working on a 36 or 40 thread Raptor Lake Refresh CPU right now to counter Zen 5? Coz that's the only thing they can do to avoid losing completely. There's almost nothing else they could do to counter the higher ST performance of Zen 5, unless they manage 6.5 GHz on Intel 4. At least an MT performance win or parity could soften the blow and keep them relevant in the minds of enthusiasts.
 

Joe NYC

Platinum Member
Jun 26, 2021
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Just saw new RedGamingTech video titled HUGE Zen5 clocks and benchmarks news, or something like that. Pretty much rehashing the previous video. I am mildly annoyed.

If the clock speed regression is minimal, that would be good.

On the other topics, 16 MB L3 for Zen 5 CCDs for Strix Halo - I am not sure if it makes sense for AMD to make a whole new CCD and strip 16 MB cache off of it. I am skeptical about it.

As far as sharing L3 and Infinity Cahce - I doubt about that one. And it if was really possible, why spend resources to chop off a part of L3, that would get extra utilization from sharing? So, all of that seems a little dubious to me.
 

Kepler_L2

Senior member
Sep 6, 2020
466
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If the clock speed regression is minimal, that would be good.

On the other topics, 16 MB L3 for Zen 5 CCDs for Strix Halo - I am not sure if it makes sense for AMD to make a whole new CCD and strip 16 MB cache off of it. I am skeptical about it.

As far as sharing L3 and Infinity Cahce - I doubt about that one. And it if was really possible, why spend resources to chop off a part of L3, that would get extra utilization from sharing? So, all of that seems a little dubious to me.
I'm not sure the L3 number is correct, but they have to make a new CCD since Strix Halo packaging is different (no IFOP/GMI).
 

Joe NYC

Platinum Member
Jun 26, 2021
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I'm not sure the L3 number is correct, but they have to make a new CCD since Strix Halo packaging is different (no IFOP/GMI).

It would be interesting if they make a new CCD, new silicon, as opposed to what AMD apparently did for Mi300, which was to just change the metal layer, and keep the original silicon (including GMI links).

If they do make a new CCD, without the GMI links, maybe it could be re-used for the next version of Mi300, if they can make it interchangeable, to change the metal layers to allow stacking instead of fanout. Otherwise, it would seem like too many types of CCDs for low volume markets.

If the CCD (minus GMI links) were to be interchangeable with Mi300, it probably does not make a lot of sense to reduce the size of L3.

And if they do reduce the size of L3, would that also preclude the possibility of adding V-Cache, with the same die as full Zen 5?
 

PJVol

Senior member
May 25, 2020
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has less L3 cache, other changes are possible (though I don't think they were ever discovered).
Such as MP2 in mobile parts or specific powersaving tech like stapm? There's a whole lot more differences.

They still have to do something about the leaky dies. That's where desktop comes in.
It's not about leakage (since long ago), but something like this, aside from the process variance: (from old Zen slides but anyway)
 
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TESKATLIPOKA

Platinum Member
May 1, 2020
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Maybe using V-cache with Strix Halo wouldn't be pointless.
Gaming performance shouldn't see a significant improvement because of IGP, but It should help power consumption a lot.
56W vs 89W average in 13 games. That's 33W difference.
Keep in mind that in laptops the difference between 16C Zen5 + V-cache vs 16C Zen5 should be lower, because of lower boost. Dragon Range lost 300MHz 5.7GHz -> 5.4GHz vs Raphael. Still, I think 20-25W would be doable.

Still, I don't think they will use It because of additional cost, but If they used It then the saved power budget could be used for IGP.
 
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Timorous

Golden Member
Oct 27, 2008
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Gaming performance shouldn't see a significant improvement because of IGP, but It should help power consumption a lot.

It will see a huge performance in all sorts of games. Just because AAA is mainly GPU limited does not mean there are no games that benefit.

Stuff like Stellaris and other paradox grand strategy, turn based 4x stuff like Civ, SIM stuff like ACC, iRacing etc will all benefit from v-cache even with a weaker GPU.

This total nonsense that v-cache helps when you have a top of the line GPU needs to die, it is entire down to what games you play.
 
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