That’s one of the benefits with the C cores, i.e. more compact and less Si area. So they are cheaper and you can have more of them at same cost compared to non-C cores.Who's gonna pay for all that Si area on N2p?
But you say the Zen5+Zen5c laptops are going to be expensive, above $999? :Most markets are too poor for all-Z5.
It's not the full stack, Zen5 starts in >$999 laptops.
Sadly not true anymore starting with N3. Cost per transistor is stalling or even going up.so price per transistor still goes down over time even if price per die area goes up.
I thought we all agree that AMDs c-Cores aren't like Competitors little Cores?! It's the same Cores packed tighter, which usually results in worse efficiency at higher clockspeeds. ZEN4c maxes out at 3.7GHz and gets worse efficiencystarting below 3GHz, Pheonix got higher Base Clocks than 3.7GHz at 35W. So we can already tell 8500G will be quite a bit slower than 8600G when they run at their default 65W TDP. It's also likely Strix would have been better/more efficient with a 8+4 design or even 12 normal ZEN5 Cores. AMD is just cutting on Die area because Microsoft is forcing everyone to integrated huge NPUs.Also, if you think cost is the reason that Zen5c cores are used, then why does both Apple, Qualcomm, and Intel use b.L in their expensive flagship models on mobile/laptop?
The point is to clock the C-cores lower, so they stay within the range where they have better perf/watt. So you get lower cost, better perf/watt, and better max MT perf within TDP. Essentially same goals as with b.L. design, even if the ”solution” for the C-core design differs compared to Little cores.I thought we all agree that AMDs c-Cores aren't like Competitors little Cores?! It's the same Cores packed tighter, which usually results in worse efficiency at higher clockspeeds.
Then we should see the same happening on DT, for both Intel and AMD CPUs.AMD is just cutting on Die area because Microsoft is forcing everyone to integrated huge NPUs.
But AMD does not usually not use the bleeding edge node. During the lifetime that Zen5 will be on the market, we can expect that the price of N3 will drop (and thus also price per transistor), as Apple et al move on to 2nm chips in 2025.Sadly not true anymore starting with N3. Cost per transistor is stalling or even going up.
Which isn't that easy because, like I wrote earlier, that point is below 3GHz. So ZEN4c will run out of this sweetspot in nearly all Consumer chips. It's good for servers in terms of power efficiency, in consumer markets you will mostly have the area saving effect, because these these 3GHz are relaxed at like 15W, and 90% of Devices tend to run their CPUs above that.The point is to clock the C-cores lower, so they stay within the range where they have better perf/watt. So you get lower cost, better perf/watt, and better max MT perf within TDP.
Looks like ZEN5 Desktop has no AI Engine at all and Intel seems to get their TOPS from iGPU XMX Engines at least with Arrow Lake. So 2024 Desktop Products should be safe. After that, I don't know what happens. I read that Panther Lake also makes sacrifices for the ×2 NPU compared to Lunar Lake.Then we should see the same happening on DT, for both Intel and AMD CPUs.
But the older Nodes where AMD is on before drop in price also. Sure N3 is cheaper in 2026 than now but N4/N5 also is, so the jump should remain the same. There is no way around the cost per transistor stall/regression.During the lifetime that Zen5 will be on the market, we can expect that the price of N3 will drop (and thus also price per transistor)
Z5c is the lead N3E product, been sampling along vanilla Z5 for a long time.But AMD does not usually not use the bleeding edge node. During the lifetime that Zen5 will be on the market, we can expect that the price of N3 will drop (and thus also price per transistor), as Apple et al move on to 2nm chips in 2025.
No that is just a symptom/result of cutting dark silicon, using higher density libraries, etc. The chips can’t clock that high.The point is to clock the C-cores lower, so they stay within the range where they have better perf/watt.
Servers with high per-core performance prioritized over core density are selling too, so I guess products for those will remain available for the time being.I expect AMD to eventually move to a single Zen “c” based CCD for server,
Yea classic isn't going anywhere.Servers with high per-core performance prioritized over core density are selling too, so I guess products for those will remain available for the time being.
Servers with high per-core performance prioritized over core density are selling too, so I guess products for those will remain available for the time being.
But that was for Zen4c, and 3 GHz is not that low for a C/Efficiency-core on laptop.Which isn't that easy because, like I wrote earlier, that point is below 3GHz. So ZEN4c will run out of this sweetspot in nearly all Consumer chips.
Intel already has such CPUs (i.e. b.L style) on the market, both on DT and laptop. Apple has it on mobile, laptop, and DT. Qualcomm and Mediatek also has such CPUs.I do agree an 8 + 16 part would be amazing, but I have seen no evidence this will ever happen and with some major changes to desktop chips happening in the next few years, it won’t happen in the future either.
are you really quoting wccftechIntel To Utilize TSMC's 2nm Process In Next-Gen "Nova Lake" CPUs, Apple a Primary Client As Well
TSMC's 2nm process has attracted significant client interest, with Apple and Intel lining up to secure the initial production batch.wccftech.com
First news about upcoming Nova Lake-S with 16P+32E to utilise DDR6 will be manufactured by TSMC's N2 process. AMD definitely will have Zen7 with 32-core ready at the same time with N2 process as well...
Yes, N2 wafer will be quite expensive, rumored about $25,000. But please go check what benefits of more advanced process, the die will not be that big compared to current 2 X CCD. From Zen5 (N4P x 2, 16-core) to Zen6 (N3P, 16-core) then Zen7 (N2, 32-core). AMD is moving to monolithics design in order to cut die size and power consumption...
It is news from Taiwan, home of TSMCare you really quoting wccftech
But we were talking about Zen5 DT. Not known for certain what process that’ll use. I’ve seem rumors saying both TSMC 4nm and 3nm.Z5c is the lead N3E product, been sampling along vanilla Z5 for a long time.
So Intel copies AMD and moves from monolitic to tiles/chiplets on DT, then AMD does the opposite. 🤣AMD is moving to monolithics design in order to cut die size and power consumption...
AMD moved to chiplets because nodes were expensive enough to make even a 2-chiplet SKU cheaper than the monolithic counterpart. Now that nodes are getting even more expensive, you expect them to go back to monolithic?AMD is moving to monolithics design in order to cut die size and power consumption...
Jebaited!So Intel copies AMD and moves from monolitic to tiles/chiplets on DT, then AMD does the opposite. 🤣
They are making a bigger CCD in server for Z6.Now that nodes are getting even more expensive, you expect them to go back to monolithic?
Guess you haven't noticed Intel is moving from 4-tile SoC down to 2-tile. AMD is moving to combine more CPU cores into one die.So Intel copies AMD and moves from monolitic to tiles/chiplets on DT, then AMD does the opposite. 🤣
No.In the future, both Intel and AMD will use 2 chiplets for desktop and notebook platform
Neither exist so ughhh.The difference is Intel is opted to integrate IOD into tCPU. That's mean upcoming Nova Lake will have bigger die size compare to AMD's 32-core Zen7.