Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[StefanR5R]

@Abwx, what if the effective bandwidth between CUs and RAM is not directly proportional to the RAM clock? The APU is complex, isn't it.

 

[adroc_thurston]

Intel should have released the 14900KS by now

They don't have the bins to do that.

 

[Glo.]

We always forget about the most important factor in the discussion about memory bandwidth.

Its always theoretical.

Usually with memory is that we do not get the full potential bandwidth available for the CPU. We lose, what? 10-20% of theoretical max bandwidth on desktop platforms?

 

[soresu]

Teensy onpackage dGPU without needing hefty cooling and power supply.

Power density is still power density, so the cooling solution will need to be beefed up to compensate for it.

Just look at the OG PS5's thicc fan and chunk of copper/aluminium it needed to cool the SoC relatively quietly.

That being said yes, the overall form factor should be reduced with it all in the same general area.

Can't wait to see the designs - might actually buy one myself.

 

[soresu]

Yep, but this round LPDDR6 and DDR6 should launch within the same 2026 year.. Of course, nobody cares about CAMM2 anymore by then


View attachment 93347

Wow, 48 Gbit DRAM comes 4 years after 32 Gbit.

A mere 50% increase in 4 years.

That's dire.

I guess 3D multilayer capacitorless DRAM is still a long ways out 😭

 

[soresu]

The thing is LPDDR6 will initially be very expensive and limited in supply, hence being relegated to flagship smartphones that are of course very expensive and sell in low volumes.

When have laptop makers been so quick to adopt a new LPDDR version?

Doubt.

More likely it will be relegated to servers and Apple Mac platforms that can better benefit and profit from it.

IMHO smartphones are at the end of their tether now in terms of visible improvement.

VR/AR HMDs still have room to breathe though.

 

[Abwx]

@Abwx, what if the effective bandwidth between CUs and RAM is not directly proportional to the RAM clock? The APU is complex, isn't it.

No doubt that there s bottlenecks within the APU since both CPU and GPU share a same RAM pool and same cache, but methink that the required bandwith for the GPU is more or less proportional to its throughput, after all the CPU work is mainly to manipulate the input/output datas for the GPU.

 

[Tuna-Fish]

I guess 3D multilayer capacitorless DRAM is still a long ways out 😭

Isn't that in pathfinder phase atm? Usually takes something like 10-20 years to go from that to mass production. I would hope that we have something better than DRAM by then.

 

[moinmoin]

Then why is it now not expected to be released until 2024H2 (likely meaning Nov-Dec 2024, or they would have said 2024Q3).

At the earnings call Lisa Su said Turin will be the Zen 5 product in the second half of the year. Beyond that there are no official (ranges of) dates. The whole reporting extending that Turin quote to all possible Zen 5 products was nothing but misquoted hot air.

See also http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...ranite-ridge-ryzen-8000.2607350/post-41149328

 

[RnR_au]

Then why is it now not expected to be released until 2024H2 (likely meaning Nov-Dec 2024, or they would have said 2024Q3).

And beaten by @moinmoin - If the mass production rumour is right, then everything matches up with a H1 20224 release and there is no mismatches with official statements from AMD.

 

[Abwx]

At the earnings call Lisa Su said Turin will be the Zen 5 product in the second half of the year. Beyond that there are no official (ranges of) dates. The whole reporting extending that Turin quote to all possible Zen 5 products was nothing but misquoted hot air.

See also http://www.portvapes.co.uk/?id=Latest-exam-1Z0-876-Dumps&exid=thread...ranite-ridge-ryzen-8000.2607350/post-41149328

Actually she talked of Zen 5 consumer products first, and when getting to Epyc she started with "Then in H2", wich mean that consumers products are eventually for H1.

Those who stated that Ryzen/Strix are for H2 are obvious manipulators since she explicitely cited Epyc as coming after consumers products.

Customer momentum for Strix is strong with the first notebooks on track to launch later this year. Looking at 2024, we are planning for the PC TAM to grow modestly year on year, weighted toward the second half as AI PCs ramp. We continue to see strong growth opportunities for our client business as we ramp our current products, extend our AIPC leadership and launch our next wave of Zen 5 CPUs.

And far later in the conference :

And then, we also see Turin, our Zen 5 product coming in the second half of the year.

 

[moinmoin]

Actually she talked of Zen 5 consumer products first, and when getting to Epyc she started with "Then in H2", wich mean that consumers products are eventually for H1.

Hm, I'm not seeing that. The whole paragraph (specifically the answer to the second question by Aaron Rakers) the quote is from is only about servers. Which part are you referring to?

 

[Abwx]

Hm, I'm not seeing that. The whole paragraph (specifically the answer to the second question by Aaron Rakers) the quote is from is only about servers. Which part are you referring to?

She talked of Zen 5 for consumers in her first intervention just before talking of the gaming segment, that s in the first lengthy paragraph, and without providing any date.

Epyc being H2 is much later in the conference, so Zen 5 consumers products launch is not related to the date given for Epyc, that s just a wild speculation
from Paul Acorn, dunno how he managed to get to this flawed assumption.

 

[RnR_au]

You can't interpret the Turin in H2 statement as anything other than being related to the server offerings. The full paragraph doesn't mention consumer products at all;

That being the case though, we also see opportunities for us to continue to grow share in the traditional server business. I think our portfolio is extremely strong. The adoption of Genoa and Bergamo, as well as our new Siena product lines are getting a lot of traction. And then, we also see Turin, our Zen 5 product coming in the second half of the year.

 

[soresu]

Isn't that in pathfinder phase atm? Usually takes something like 10-20 years to go from that to mass production. I would hope that we have something better than DRAM by then.

Yeah.

Trouble is that any alternative but STT MRAM is probably not there yet either, and certainly not there in terms of 3D multilayer devices which will be a necessity to scale further at this point.

I guess we'll see which gets to the finish line first.

 

[igor_kavinski]

AMD really wants to avoid the Osborne effect so not gonna talk about Zen 5 until they are sure they have enough volume to make a beastly profit. It doesn't help them at all to have a shortage of Zen 5 chips, people dying to buy them and shunning Zen 4 chips and on top of that, frickin' scalpers making all the profit.

 

[S'renne]

AMD really wants to avoid the Osborne effect so not gonna talk about Zen 5 until they are sure they have enough volume to make a beastly profit. It doesn't help them at all to have a shortage of Zen 5 chips, people dying to buy them and shunning Zen 4 chips and on top of that, frickin' scalpers making all the profit.

More than 6 months later to only find Zen 5 laptops in selected models only lol

 

[FlameTail]

Doubt.

More likely it will be relegated to servers and Apple Mac platforms that can better benefit and profit from it.

Apple has been traditionally slow in adopting new LPDDR versions, for both Mac and iPhone. Neither the new iPhone 15 Pros or the M3 Macbooks use LPDDR5X. They are all still using LPDDR5.

IMHO smartphones are at the end of their tether now in terms of visible improvement.

VR/AR HMDs still have room to breathe though.

The first to adopt the new LPDDR5T/5X-9600 has been some flagships Android's from China.

 

[S'renne]

Apple has been traditionally slow in adopting new LPDDR versions, for both Mac and iPhone. Neither the new iPhone 15 Pros or the M3 Macbooks use LPDDR5X. They are all still using LPDDR5.

The first to adopt the new LPDDR5T/5X-9600 has been some flagships Android's from China.

I wonder how would they allow us to choose RAM capacities, because 32GB and above are fairly pricey on laptops, and 192 bit or 256 bit might make SK Hynix's RAM package a bit more difficult to work with...maybe not..

Edited for clarification.

 

[adroc_thurston]

because 32GB and above are fairly pricey on laptops

Not really, no.
32GB L5x piles on the likes of modern thinkpads are reasonable money.

 

[Philste]

At the earnings call Lisa Su said Turin will be the Zen 5 product in the second half of the year. Beyond that there are no official (ranges of) dates. The whole reporting extending that Turin quote to all possible Zen 5 products was nothing but misquoted hot air.

Those who stated that Ryzen/Strix are for H2 are obvious manipulators since she explicitely cited Epyc as coming after consumers products.

You can't interpret the Turin in H2 statement as anything other than being related to the server offerings. The full paragraph doesn't mention consumer products at all;

In the earnings call itself they only talked about Turin, but 4-5 hours after the earnings call Paul Alcorn from Toms Hardware made a Post that an AMD Rep (NOT Lisa) just confirmed to him that Desktop is H2. What is so difficult to understand about it?

And this time it's not some random Chinese forum dude leaking something. A managing Editor of Tom's Hardware posting something completely made up and claiming an AMD Rep said it to him would have definitely triggered a press release with clarification from AMD. So it's H2, period.

 

[RnR_au]

In the earnings call itself they only talked about Turin, but 4-5 hours after the earnings call Paul Alcorn from Toms Hardware made a Post that an AMD Rep (NOT Lisa) just confirmed to him that Desktop is H2. What is so difficult to understand about it?

And this time it's not some random Chinese forum dude leaking something. A managing Editor of Tom's Hardware posting something completely made up and claiming an AMD Rep said it to him would have definitely triggered a press release with clarification from AMD. So it's H2, period.

Fair enough. Just odd that Paul didn't make a 'proper' post on their website but just tweeted the news.

 

[Trovaricon]

No doubt that there s bottlenecks within the APU since both CPU and GPU share a same RAM pool and same cache, but methink that the required bandwith for the GPU is more or less proportional to its throughput, after all the CPU work is mainly to manipulate the input/output datas for the GPU.

That isn't true, in all existing AMD's APUs to this day GPU cluster is directly connected to the fabric. GPU has its own L2 and cannot utilize L3 which is part of CPU cluster. See https://chipsandcheese.com/2023/09/16/hot-chips-2023-amds-phoenix-soc/

I really hope that non-Halo Strix Point has either beefed up capacity of L2 or that AMD finally decouples L3 from CPU cluster and transforms it into a SLC from topology point of view. I believe it would also bring a benefit of reduced power consumption.

 

[adroc_thurston]

I really hope that non-Halo Strix Point has either beefed up capacity of L2

No.

AMD finally decouples L3 from CPU cluster and transforms it into a SLC from topology point of view

Oh god no AMD L3 is fine as is.
Don't touch what works.

I believe it would also bring a benefit of reduced power consumption.

Yeah which is why the og-og STX1 from many years ago had 16 megs of MALL.

 

[StefanR5R]

@Abwx, what if the effective bandwidth between CUs and RAM is not directly proportional to the RAM clock? The APU is complex, isn't it.

methink that the required bandwith for the GPU is more or less proportional to its throughput, after all the CPU work is mainly to manipulate the input/output datas for the GPU.

But there is more to it. Do we know whether or not Phoenix's fabric between IMC and iGPU is designed to follow along when the DDR5 clock is upped from e.g. 5200 to 7200 MT/s? (And to get back to topic, whatever Phoenix's design targets/ design limits WRT various clocks in the datapath were, they are certainly updated in Strix Point one way or another…)