Apple does not have higher IPC than Intel or AMD. They do have the best TSMC silicon but that's it.Why does it matter? If Apple is able to have higher IPC than AMD/Intel, it makes up for the clock speed disadvantage.
For 2 years.That would give AMD the performance crown across all categories for 4-6 months
Granite Ridge exists until Medusa DT.After Arrowlake releases, AMD should release a Zen 5 refresh on TSMC N3P.
Wouldn't they just release the 3D cache version?After Arrowlake releases, AMD should release a Zen 5 refresh on TSMC N3P.
Excuse me, what?Apple does not have higher IPC than Intel or AMD. They do have the best TSMC silicon but that's it.
This could have been fixed by the respin if occured, unless there was a flaw at DTA/STA.That s not much difficult to spot what went wrong with RDNA3, the chips still clock quite high but methink that for some reasons there were some critical circuitries within the GPU that didnt clock accordingly with the projected stock voltage.
March 2025 for TSMC N3P silicon. A 16C/32T Zen 5 CPU with a 95w TDP would be brutal for Intel no matter how crazy Arrowlake performance could be :
Well we don't have to wait long to get some actual potential proof, Strix and Strix Halo should put to rest whether or not there was an actual issue with RDNA3 soon enough.That s not much difficult to spot what went wrong with RDNA3, the chips still clock quite high but methink that for some reasons there were some critical circuitries within the GPU that didnt clock accordingly with the projected stock voltage.
It can be only 10% of the whole chip but they had to increase voltage by about 10%
for the whole to get the flawed parts working with inconditional stability, and at this rate this did increase the comsumption by 20% wich led to the missed perf/watt target, guess that it should be the main fix that will be done with RDNA3.5.
and with Medusa, they'll loose the performance crown? I don't get it lolFor 2 years.
Until Medusa.
Granite Ridge exists until Medusa DT.
He's saying that Granite Ridge will be unsurpassed until Medusa/Zen 6 desktop surpasses it, meaning Intel will have nothing to compete with Zen 5.and with Medusa, they'll loose the performance crown? I don't get it lol
Anyhow, Apple clocking their cores higher is needed to compete in desktop. This is where AMD and Intel have huge lead.
This is not how (or with whom) Apple competes. They are a systems seller and a software and service provider.Why does it matter? If Apple is able to have higher IPC than AMD/Intel, it makes up for the clock speed disadvantage.
Reaching Apple's IPC level does not guarantee reaching Apple's efficiency level.
Would be interesting if folks made measurements once Zen 5 based mobile devices are out. (In the past, there has been lots of idle talk at a level of benchmark-score-divided-by-power-limit, and disappointingly little in the way of actual measurements.)The first bunch of Zen 5 based products will be MCMs with 4nm chips. So there is that.
RDNA3 timeline:This could have been fixed by the respin if occured, unless there was a flaw at DTA/STA.
And while I generally agree that the clocks seem okay, there can be several causes.
I'd say an occupancy issue on the GCD side hampering performance scaling, plus the off-die cache / logic / interconnect subsystem came out quite the power-hog.
The former is probably fixed in rdna 3.5-4, and got rid of the latter until it's ready. Both can't be fixed just upon respin
Are you sure this was adressed to me?RDNA3 timeline:
.....
So full Strix Point should be around 4k points in TS. Thats RX 6400 desktop territory, without its VRAM capacity limitations.This is the Z5 thread, but if we are to talk about RDNA 3, Xino shared that STX 12 CU (Full implementation is 16 CU) 22 - 24W scores ~3150 TS.
Phoenix was around 2400? At the same wattage.
So that's a nice boost. Maybe the power scaling and clocking issues are fixed on RDNA 3.5, alongside the backported sALU.
Middling at best. MTL Arc already does that at elevated power levels.So full Strix Point should be around 4k points in TS. Thats RX 6400 desktop territory, without its VRAM capacity limitations.
For such a cache/bandwidth starved implementation of RDNA, that's really good. AMD basically giving an integrated RTX 3050 35 - 50W with every STX SoC, but without the VRAM bottleneck.So full Strix Point should be around 4k points in TS. Thats RX 6400 desktop territory, without its VRAM capacity limitations.
And performs about the same as PHX right now.Middling at best. MTL Arc already does that at elevated power levels.
Apple does not have higher IPC than Intel or AMD. They do have the best TSMC silicon but that's it.
Imagine a Strix Halo laptop with 256 GB RAM (made possible thanks to the 256 bit bus).
Indeed! And some tiny RDNA4 features.the fix is what RDNA3.5 is about!
No, it means they're competing with themselves.and with Medusa, they'll loose the performance crown?
You're forgetting about Lunar Lake.And performs about the same as PHX right now.
STX catching up in TS means in actual games it should far exceed.
Different part for different segment.You're forgetting about Lunar Lake.