I don't know how easy it is to open a metallic HP laptop using an Intel U series CPU but my plastic HP one was darned hard to open up when I took it to a shop to upgrade its RAM to 32GB. It was shut really tight and the force that the guy had to apply, had him visibly nervous. If I had tried to open it, I definitely would have snapped something off the plastic underside cover and then I would have had to either glue or tape it shut.The last laptop I opened up was an Aspire 7 which is simple but takes a lot of screws to open up. If I need work done on my XPS laptop I image the computer and wipe it before sending it in.
That's why I don't bother with most laptops. If I have to take 10-30 screws off the bottom and then deal with multiple stiff clips I'd rather give the laptop to an authorized repair center. It's over engineered for no real reason and doesn't add to the rigidness of the chassis.I don't know how easy it is to open a metallic HP laptop using an Intel U series CPU but my plastic HP one was darned hard to open up when I took it to a shop to upgrade its RAM to 32GB. It was shut really tight and the force that the guy had to apply, had him visibly nervous. If I had tried to open it, I definitely would have snapped something off the plastic underside cover and then I would have had to either glue or tape it shut.
Mark, to be honest here I don't appreciate what you are doing.First "Zen 4 leaves Intel's server, workstation, mainstream and mobile dead in the water unless they can pull off one big surprise".
I say this or more appropriate. In a week or 2, I will have a fully functional 9654 Genoa to help prove this(its partially assembled now). As far as TSMC 3mm for Intel, lets talk about that once we at least have ES leaks.
First, this IS an AMD thread. Second, Do you know how sick I am of hearing that "Intel ha something great coming soon", and it never arrives with performance as claimed ? I would talk about that, but its off-topic. But that is 100% why I say this. The "trick me once, shame on me,, trick me twice, shame on you" is what applies here. I am so sick of Intel promises and failure to deliver, I can't tell you. And we are speculating on AMD future, not Intels. And I am not sure what your last sentence applies to, but if its in an Intel thread, DON'T bring it up, and its OFF-TOPIC, and the only people that may not have appreciated it most likely were Intel supporters.Mark, to be honest here I don't appreciate what you are doing.
You do this constantly, some one is speculating about future competition between Intel and AMD products...
And then you bring up how Intel is doing terribly now in competition with Zen 4, and how we can't speculate about Intel products for one reason or another.
I kid you not, it's a pattern. It doesn't adding anything really to the conversation either. And based on the response last time, it's something most in Anandtech do not appreciate.
Not quite.I recall this. Was it in the news this January or on Linus Tech Tips?I have to look into it and see how it works but I'm guessing it sucks in air from outside the chassis and blows it onto the chip?
The slitted vents at the top where the panel meets the main body that also flows to the back portion of the laptop? I'm sure this is filtered at some stage in the uptake process? I was thinking the vents would be designed on the sides but there's a greater chance of larger debris making its way filters or not.Not quite.
It's still using a copper base which they recommend placing on a vapor chamber.
The internal MEMS chips create jets of air that draw air in from thin, long vents at the top of the device to hit the copper base so fast that even boundary air directly on the surface of the copper is blown away while fans usually do not produce enough speed of airflow to manage this which reduces efficiency of cooling radiators.
The air is then expelled out a thin slit on the side of the device, which presumably you will want to engineer the layout of the board so that it is close to an air vent.
The jets work at such velocity that they can work with relatively low perf degradation even with dust filters in play - either way I'm sure the engineers will work it out.The slitted vents at the top where the panel meets the main body that also flows to the back portion of the laptop? I'm sure this is filtered at some stage in the uptake process? I was thinking the vents would be designed on the sides but there's a greater chance of larger debris making its way filters or not.
This is a thread about Zen 5 products. I'd argue speculating about Turin vs Granite Rapids is far more on topic than Genoa vs Sapphire Rapids.First, this IS an AMD thread.
Lmao, sure. I seem to recall you accusing me of being a delusional fanboy for agreeing with what was ultimately a 100% accurate Alder Lake leak. But of course, somehow the same specs you considered impossibly, delusionally good became trash and disappointing when you had to deal with them being real. Amazing how that seems to work...Second, Do you know how sick I am of hearing that "Intel ha something great coming soon", and it never arrives with performance as claimed ?
Neither is any less speculation than the other. Not sure what mental gymnastics you're performing to reach this conclusion.We even have preliminary (possibly fake, but maybe real) of Zen 5 performance. THAT IS SPECULATION. What you have is "pie in the sky" hopes.
I was responding to someone who literally referencing the Intel competition products. I didn't know it wasn't allowed to reference the competition in this thread. Will I get banned for spelling out Intel now? Yes, part of AMD's future is the competition, Intel.First, this IS an AMD thread. Second, Do you know how sick I am of hearing that "Intel ha something great coming soon", and it never arrives with performance as claimed ? I would talk about that, but its off-topic. But that is 100% why I say this. The "trick me once, shame on me,, trick me twice, shame on you" is what applies here. I am so sick of Intel promises and failure to deliver, I can't tell you. And we are speculating on AMD future, not Intels. And I am not sure what your last sentence applies to, but if its in an Intel thread, DON'T bring it up, and its OFF-TOPIC, and the only people that may not have appreciated it most likely were Intel supporters.
Lastly, I don't appreciate Intel supporters coming into an AMD thread and saying how great Intels future products are going to be, namely in this case YOU, and complaining about my posts that ARE ON TOPIC. You can say those things since a speculation thread, but don't whine when people don't agree with you.
Edit: would you like to come up with any evidence that where is an REAL (as in ES chips or QS chips) possibility of your claims ? We even have preliminary (possibly fake, but maybe real) of Zen 5 performance. THAT IS SPECULATION. What you have is "pie in the sky" hopes.
If you don't like what I say, don't reply to me.I was responding to someone who literally referencing the Intel competition products. I didn't know it wasn't allowed to reference the competition in this thread. Will I get banned for spelling out Intel now? Yes, part of AMD's future is the competition, Intel.
And off a tangent, everything we are talking about is literarily a year or more into the future. And what products that were hyped up failed to deliver with performance? SPR was supposed to be around Milan level, it's now slightly lower. RPL had better than expected ST gains. ADL was originally thought to be a 5900x competitor. RKL did end up performing worse than expected, but again marginally worse, in ST. Intel constantly struggles with execution of timeline, not really performance (unless they can't execute a node jump lol).
No barrage of "Intel supporters" are flooding this thread with how great Intel future products are. The vast, vast majority of the discussion is about Zen 5. I personally talked about what I expect in Zen 5 in this thread as well. I'm not complaining about what you not agreeing with me, I debated plenty of people who do that on reddit and here as well. What I am tired of is you repeatedly hijacking any conversation about speculation of future products and connecting them back to how Intel is doing bad right now, and how future Intel leaks are not valid, for one reason or another. This isn't even Intel thread specific either, IIRC last time you did this in the Zen 4 specifications thread, you got shoo'd away there too. Your comments are on topic only in the most literal of sense. They don't add anything of value when you do this.
Zen 5 doesn't even have ES or QS chips yet, but you want me to support ARL rumors with those? And besides, how is the run of the mill 15% IPC gain a "pie in the sky" hope? That's a normal IPC gain from a new Intel architecture.
The funniest part about this is, I didn't even bring it up until someone else brought up the competition. And based on who that someone else is upvoting, he looks to like AMD's chances more than me. Now I'm not complaining, I'm no stickler for upvotes or likes. But I find it hilarious that you pretend there's some conspiracy of Intel supporters coming into AMD threads to hijack the discussion about how great Intel products are going to be.
To wrap it up, Mark, just please stop responding to me if thats what you are going to respond to me with. I don't appreciate it.
I think it's very likely that we'll see IPC being more or less equal between Lion Cove and Zen 5, maybe +15-20% each. Tbh, think the hype train is getting a bit out of control there again. Intel 3 vs N4 is probably close enough to a wash, so Turin will probably enjoy a moderate lead, but not the ~2x they have today.Yes
A 30% per core improvement should put AMD in the lead for single core IMO. I'm guessing LNC IPC is going to be more in the league of ~15% IPC, the same per core IPC improvement we see with previous 'new' Intel architectures. But clocks should be much, much better with ARL. ARL is on Intel 20A for their compute tile. On desktop it's 3nm... This is facing the 4nm of Zen 5.
For server, RWC in GNR should be considerably less powerful than Zen 5, on a per core basis. However, if RWC+ is a decent gain. or Lion Cove is used in GNR, then the difference shouldn't be too bad. And this isn't just fanfic either, Gelsinger himself said GNR uses a 'new core' and GNR as a product changed so much they wanted to change the codename of the product. Plus, server also has some reprieve, it should be on Intel 3, which at the very least should be better than the TSMC 4nm node Zen 5 uses even if it's not a true 3nm class node.
Nothing should be left 'dead in the water', nor does Intel really need a 'big surprise'. As long as LNC is a run of the mill architectural uplift, like GLC was or SNC was before it, Intel should be fine, if not in the lead but competitive. At the very least, it should be in a much better state they are right now, esp in server lol.
Lastly, this doesn't even hinge on Intel's own internal nodes, since rumors claim they are contracting TSMC for 3nm. All the better nodes should allow for, both in desktop and server especially, is better clocks in clock limited workloads (Server and desktop MT) and potentially better ST as well, though as we have seen with Intel 14nm, and now Intel 7, that's not a guarantee lol.
IDK about a hype train but II heard Lisa is going to spit acid on Jensen and make him disappear in a puff of smoke and trained imps are going to destroy Nvidia's internal pricing documentation driving the price down.Tbh, think the hype train is getting a bit out of control there again. Intel 3 vs N4 is probably close enough to a wash, so Turin will probably enjoy a moderate lead, but not the ~2x they have today.
Actually good point, Zen was designed to be more like Intel Core architecturally. For instance, SMT, op cache, etc., after the beating Bulldozer took.Some will say that benchmarks using the same code for everything like Geekbench (at least within versions like 5.0, 6.0, etc.) is superior to SPEC for this reason, but when there are major changes in an architecture (like P4 to Core, Bulldozer to Zen, x86-32 to x86-64) you often need to update the compiler to fully exploit them and you just won't see the full effect with that - though to be fair, also won't see the full effect until the applications you care about have to updated.
LNC is rumored to be 8 wide
Thinking a bit further ahead, I'm wondering what AMD does for the gen after Turin. Looking at PCIe 6.0 timeline, so due for an IO die revamp (opportunity for new packaging tech), and N3 (or even N2?) will provide good process gains. Might be when we see the next big core bump as well.
Which is why I am quite skeptical of Zen 5 rumors. Zen 5 is not about increasing decode width, dispatch, PRF, L2, BTB, etc. It is quite a different machine architecturally.
What do you mean releasing so soon? Zen 5 is in development since 2018. Six years ! that's one year longer than the original Zen program.AMD actually said the front end will be wider about 2 years ago. I doubt AMD will invest too much effort while releasing it so soon. After all it's still part of the Zen arch family. It's the successor to Zen6 that's expected to be radically new. Unless AMD changes their mind again and introduces a Zen7 instead of a new arch family.
You are forgetting they wasted a lot of time to design it for both N4 and N3.What do you mean releasing so soon? Zen 5 is in development since 2018. Six years ! that's one year longer than the original Zen program.
[Zen5] is only on N3/(3nm).You are forgetting they wasted a lot of time to design it for both N4 and N3.
Mmm, don't mind me mate.You are forgetting they wasted a lot of time to design it for both N4 and N3.
Zen 5 is on N5 family and N3 family.[Zen5] is only on N3/(3nm).
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Now that is a truly lost "art" form.People are too used to AOL's chatrooms.
Meant that N2 bit to refer to the compute dies. Might not have made that clear originally.There's no need for the IO die to be on the same node as the CCD, one lower will do. According to AMD's slide, Zen6 starts with N3. There's a possibility of Zen6+ to be N2 if it follows the same upgrade scheme as Zen4 and Zen5. Looking at the timeline N2 will be in mass production in 2025. It's possible but not warranted at this time. So the IO die will most likely be on N4.
It seems Zen was designed to be an AMD copy of Haswell/Broadwell. No exotics. Proven solutions only. AMD-sourced way.Actually good point, Zen was designed to be more like Intel Core architecturally. For instance, SMT, op cache, etc., after the beating Bulldozer took.
With Zen 5, at least from gossips I hear, AMD is designing a much more different machine compared to Intel P Core and OG Zen (1-4).
Which is why I am quite skeptical of Zen 5 rumors. Zen 5 is not about increasing decode width, dispatch, PRF, L2, BTB, etc. It is quite a different machine architecturally.
A return to Bulldozer kind of rethinking the Core uarch. It could bite AMD again who knows.
There are no references in the open though, not that I heard much beyond this statement anyway.
This time AMD has a decent enough team working on compilers and toolchains, especially LLVM.
But like you mentioned it will be interesting if traditional benchmarks will even see big enough gains. Linux 6.5 window will come soon and amd_edac rework just got merged, so we will be seeing some hints.
It is not so bad actually. If you use their AOCC it is quite performant and up to date. The main issue is that AMD has been so secretive that patches land AFTER the product has launched.Besides that, AMD is extremely slow with their SW support. For example, GCC support for Zen 4 (including Genoa) is scheduled to be available in April's GCC 13.1. This means the H2 2023 Linux distros *might* start to pick it up.
This is the interesting thing about Zen 5. How will they rework the core uarch while ensuring legacy workloads wont have a regression.OTOH, AMD still call it "Zen". So it *should* be a continuation of the balanced Intel Core-compatible way. Fingers crossed on a 5-6 wide deeper version of Zen 4 achieving 15% IPC rather than another radical IA-64/NetBurst/K9/K10/Niagara/Bulldozer.
AOCC is a niche compiler just like ICC. It might be a good choice for a large HPC project after a great deal of testing, although it remains an experimental odd choice for the rest of the applications.It is not so bad actually. If you use their AOCC it is quite performant and up to date. The main issue is that AMD has been so secretive that patches land AFTER the product has launched.
Intel on the other hand has been sending GNR, EMR, MTL patches for almost a year now towards GCC/LLVM/Kernel and other repos.
This exposes a lot the internals of upcoming CPUs but then you have Day 1 support in important Software and Toolchains and launch benchmarks turn out great.
AMD tried submitting patches upstream for their upcoming HW on multiple occasions but since nobody can see their documents patches get stuck in review for months until after launch when documents are released.
This is the interesting thing about Zen 5. How will they rework the core uarch while ensuring legacy workloads wont have a regression.
N4/N3 offers significant density and efficiency gains that they can just tack on more resources to the core and call it a day. Or they could redesign the core to make it shine in the workloads of the next 4-5 years. AMD has to address competition from non x86 CPUs as well which are not burdened by this constraint.
In contrast to what someone said few posts above, the physical implementation is the easy part. Getting your HLS and running through the simulations until you find the optimal design that fits all these scenarios is the harder part. Fortunately, these days folks have access to super computers and such which greatly speeds up the process, however the design complexity also exploded. Nevertheless, I would say chances of another Bulldozer are still there .
How has this been done historically? I mean, it seems the transistor budget these days is rather decent, at least as long as AMD is using TSMC, is there any reason why they are not slowly just adding functions for what they think the future needs? That being whether or not they have planned a radical architecture shift in the next few generations, surely slowly adding that in would be useful? I realize that its being designed several years ahead, so whatever generation is in its infancy right now will probably have some AI/ML functions added just to be safe (despite the GPUs doing the main work)?This is the interesting thing about Zen 5. How will they rework the core uarch while ensuring legacy workloads wont have a regression.
N4/N3 offers significant density and efficiency gains that they can just tack on more resources to the core and call it a day. Or they could redesign the core to make it shine in the workloads of the next 4-5 years. AMD has to address competition from non x86 CPUs as well which are not burdened by this constraint.