Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Ghostsonplanets]

What's in the water? So many sounding nutty.

Computex infected the water sources everywhere.

 

[xilli_fiberbit]

The chipsets will be nammed X870 and B850 to match Intel number, so no 7xx series

 

[Mopetar]

If I've learned anything from the last several pages it's to stay away from bath salts.

 

[CakeMonster]

So if I understand correctly the IOD and the chipset appears to be the exact same hardware as two years ago, I guess that's fine.. just a bit disappointing with regards to evolution. I hope the jumps for Z6 are bigger to make up for that.

 

[Kepler_L2]

So if I understand correctly the IOD and the chipset appears to be the exact same hardware as two years ago, I guess that's fine.. just a bit disappointing with regards to evolution. I hope the jumps for Z6 are bigger to make up for that.

Same situation as Zen3. The fun stuff is the new core.

 

[adroc_thurston]

I hope the jumps for Z6 are bigger to make up for that.

Well the SOC architecture is all different.
Nothing else should change on DT otherwise.

 

[dr1337]

It would be funny if all the rumors are wrong and Zen5 is actually the 'Zen2' of AM5. New IO die, probably 3D stacked and with LLC, and 32c for the 8950x, but only milder IPC and clock gains.

But I do think its more likely they go all in on optimizing right now and do the IO transition on Zen6. Zen4 as a uArch seems extremely ripe for widening.

 

[adroc_thurston]

It would be funny if all the rumors are wrong

No.

and Zen5 is actually the 'Zen2' of AM5

No.

New IO die

No.

probably 3D stacked and with LLC

This will remain a specialty option till the end of the decade.

but only milder IPC and clock gains.

Clock gains are indeed single digits.

 

[Mahboi]

So if I understand correctly the IOD and the chipset appears to be the exact same hardware as two years ago, I guess that's fine.. just a bit disappointing with regards to evolution. I hope the jumps for Z6 are bigger to make up for that.

They are.
Z5 is the big core Tock/large remake. Promises to be much bigger than Z2/Z3/Z4 were.

Z6 is basically everything BUT the core. New I/O, new uncore, new segments...
Both of them will really throw AMD into a new future.

 

[Det0x]

Guess i will be getting a new ferrari w16 engine in a few weeks then since i'm bored with my 8500G, 8700G, 7800X3D, 7950X and 7950X3D


Videocardz made a post about it also

AMD Ryzen 9000 desktop series with 16, 12, 8 and 6 Zen5 core configs reportedly launches in July - VideoCardz.com

AMD to unveil the desktop Ryzen 9000 series next week, launch expected in July Chiphell leaker wjm47196 claims that there is no change to the core count for the new Ryzen desktop series. A new rumor comes from wjm47196, who left a cryptic message on the Chiphell forums. This leaker has provided...

videocardz.com

 

[dr1337]

No.

No.

No.

This will remain a specialty option till the end of the decade.

Clock gains are indeed single digits.

Is there any reason why you ignored the entire second half of my post?

Yeah you can say No over and over to make me look bad for no reason but I don't disagree with you...

 

[adroc_thurston]

Is there any reason why you ignored the entire second half of my post?

Yeah cuz being an obnoxious realist™ is funny.

Yeah you can say No over and over to make me look bad for no reason

It doesn't look bad besides the V$ bit, that's too niche to be auto mainstream for a while.

 

[maddie]

This will remain a specialty option till the end of the decade.

Concerning 3D stacking.

Why?

Costs? Lack of capacity? Yield penalty?

 

[IEC]

I look forward to upgrading to the Zen5 based X3D gaming chip in the fall.

 

[Ajay]

I look forward to upgrading to the Zen5 based X3D gaming chip in the fall.

Supposedly much later than that. Still, that's what I'll go with - much later when the prices start coming down.

 

[adroc_thurston]

Costs?

No.

Lack of capacity?

Sort of.

Yield penalty?

Not quite.
The main issue with d2w hybrid bonding is that it's a physically slow process.
Good for server and HPC, but high unit volume CPU/APU stuff is a no-go.

 

[DrMrLordX]

I thought the current consensus (high confidence since we are so close to the announcement) was -5% PPC and SMT4

Lol SMT4 confirmed!!!

SMT 8 confirmed.

who needs e-cores when each p-core is so wide it can run 8 concurrent threads.

Oh wait fr

It makes sense given AI AI AI...

I already posted a Shakira video, do I need to go for Bumblebee Man next? Ay ay ay no me gusta!

It would be funny if all the rumors are wrong and Zen5 is actually the 'Zen2' of AM5. New IO die, probably 3D stacked and with LLC, and 32c for the 8950x, but only milder IPC and clock gains.

FYI Zen5 CPUs will be 9-series, not 8-series. 8-series is reserved for things like Hawk Point which is already on the market.

 

[dr1337]

FYI Zen5 CPUs will be 9-series, not 8-series. 8-series is reserved for things like Hawk Point which is already on the market.

I mean maybe but no one really knows officially until computex. So until then maybe if that dumb ryzen AI rumor is true then possibly all Zen5 will get that branding and number scheme instead.

 

[Joe NYC]

The main issue with d2w hybrid bonding is that it's a physically slow process.
Good for server and HPC, but high unit volume CPU/APU stuff is a no-go.

If AMD figured either of:
a) cooling of the chip if entire CCD is covered by V-Cache
b) put V-Cache under the CCD

Then Wafer on Wafer stacking could be used, and it would overcome challenges you mentioned.

As far as "known good die", if V-Cache was so highly redundant that it would be close to 100%, yield would be affected minimally.

 

[adroc_thurston]

As far as "known good die", if V-Cache was so highly redundant that it would be close to 100%, yield would be affected minimally.

The stacking itself may fail.

 

[CakeMonster]

With regards to X3D chips and the cache, is the assumption that the inter-CCX latency is still high between two of them, and possibly even more so relatively if they both have extra cache? I have struggled to figure out the explanation that AMD couldn't find a performance benefit from two equal CCX's with extra cache, but if its the inter-communication that was the issue all along that kind of makes sense.

I don't like the more complex thread prioritization logic anyway versus 'simple' P/E (freq vs cache complicates the algorithm), so I'd possibly be prepared to eat the cost and latency between CCX's anyway if the dual full sized versions were available.

 

[leoneazzurro]

The problem is not mainly the inter-CCD communication, but the fact that the extra cache works, in the consumer space, only for some workloads that in contrast are not heavily multi-threaded (basically, gaming and not a lot more). We have to add that adding V-cache on the second CCD would have limited the all-core boost (due to the added thermal resistance of the cache die) so, in short, adding the cache on the second CCD of a 7950X3D would have brought very limited performance boost (if not a regression in some cases) in consumer applications, in front of increasing the production costs (one more cache die + die thinning + hybrid die bonding). That is, not a smart idea.
HPC space is different, there you have in some cases some heavily threaded workloads that benefit substantially of the extra cache, so in that environment the presence of the V-cache on all CCDs is justified (and even there, it depends a lot on the applications you must run).

 

[Mahboi]

With regards to X3D chips and the cache, is the assumption that the inter-CCX latency is still high between two of them, and possibly even more so relatively if they both have extra cache? I have struggled to figure out the explanation that AMD couldn't find a performance benefit from two equal CCX's with extra cache, but if its the inter-communication that was the issue all along that kind of makes sense.

There's 2 cases where V$ does nothing at all:
- high computation, low data amounts
Normal cache works just fine for those and the extra cache is never needed
- low computation, very high data amounts
Even V$ will get overloaded and ends up being not more or less useful than normal cache

The problem is that these two cases represent an extremely high amount of programs.

The one sweet spot is when you have a higher need for data needed in cache that'll also need a large amount of computation. The typical example being of course games, where you have tons of logic that gets re-run every frame, but that logic isn't so heavy on data usage that it needs over 100Mo.

So was there a point in making both CCDs 3DV$? Sure, marketing.
But was there a technical advantage? Not really. The tech's just a nice bonus, but it's far from being a magical silver bullet.
And a ton of things can also be surprising once certain ucode optimisations come through:

Linux 6.6 Looks To Be Very Lucrative For AMD Server Performance - Phoronix

www.phoronix.com

V$ used to be the best in class with latency among EPYCs, became the worst.
Bergamo was 2nd, stayed 2nd, while Genoa went from worst to best.
Just from upgrading Loonix 6.5 to 6.6rc1.

V$ is not as all-around good as one might think. It also forces the power/temperatures down a bit because it's fragile heatwise.
It's amazing for gaming, less so for most other stuff.

 

[ToTTenTranz]

They want STX for very much other reasons.

Such as?

This will remain a specialty option till the end of the decade.

Why haven't we seen APUs with V-cache for its iGPU though?

People would kill for low power APUs whose GPUs don't suffer from massive bandwidth bottlenecks in gaming.
How much would a Strip Point with 32MB Infinity Cache sell for, to fit premium thin&lights and handhelds? $300 or more?

 

[igor_kavinski]

That is, not a smart idea.

AMD needs to have a shared L4 V-cache for both CCDs.