Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[SpudLobby]

APX is just aa64: x86 edition. Except the whole "cleaning the ISA" part.
Wasted opportunity really.

Honestly surprised at this admission but yes, correct.

 

[biostud]

It seems that way, since AMD extended the time AM5 will be supported to 2027 (from 2025).

But I wonder if there is a possibility of something like Strix Halo Zen 6 launching that will start a new, higher end socket, with more memory channels supporting CAMM2 memory...

As long as they have the 3D models, I don't think they have to be first movers going for new memory standards, but eventually it will make sense.

 

[tsamolotoff]

I personally believe AMD should have split Ryzen into two different lines - something like Ryzen Gaming (with all x3d chips) and Ryzen SoHo to differentiate the purpose of those SKUs, but since they CBA to add GMI-W, asking that would be a tall order for AMD.

 

[Joe NYC]

As long as they have the 3D models, I don't think they have to be first movers going for new memory standards, but eventually it will make sense.

I think it also depends on the success of Strix Halo. If it really catches on, AMD will have incentive to build up on it and make a new socket for it, and sell it as an APU as well.

And once you have a new socket, you can introduce desktop chips for it as well.

As of now, bandwidth is not a big bottleneck for desktop, and 4 memory channels would not add as much to strictly desktop CPUs vs. APU with a beefy GPU part.

 

[inf64]

I have to say I'm disappointed with the IPC numbers, but there is something odd with that slide AMD presented: they didn't do 1T normalized clock speeds but just listed random workloads with no mention of 1T or nT. Do we have data on this in the endnotes? (sorry if I missed posts about this)

I wonder if SMT uplift is lower on Zen 5 and those nT results in the mix are kinda lowballing it (ST IPC) a bit. For all the changes they made, I expected much bigger IPC uplift.

 

[Racan]

Hopefully this means that Zen6 will also be on the AM5 platform. To me there is no reason to upgrade from Zen4 to Zen5.

Same here. I’m hoping we get Zen 6X3D support, until then I’m pleased with my 7800X3D.

 

[Timorous]

I have to say I'm disappointed with the IPC numbers, but there is something odd with that slide AMD presented: they didn't do 1T normalized clock speeds but just listed random workloads with no mention of 1T or nT. Do we have data on this in the endnotes? (sorry if I missed posts about this)

I wonder if SMT uplift is lower on Zen 5 and those nT results in the mix are kinda lowballing it (ST IPC) a bit. For all the changes they made, I expected much bigger IPC uplift.

The gaming numbers hint at an uplift greater than 16% for gaming workloads at least.

 

[leoneazzurro]

I have to say I'm disappointed with the IPC numbers, but there is something odd with that slide AMD presented: they didn't do 1T normalized clock speeds but just listed random workloads with no mention of 1T or nT. Do we have data on this in the endnotes? (sorry if I missed posts about this)

I wonder if SMT uplift is lower on Zen 5 and those nT results in the mix are kinda lowballing it (ST IPC) a bit. For all the changes they made, I expected much bigger IPC uplift.

All the tests were n-thread, no 1t tests.

 

[Joe NYC]

I personally believe AMD should have split Ryzen into two different lines - something like Ryzen Gaming (with all x3d chips) and Ryzen SoHo to differentiate the purpose of those SKUs, but since they CBA to add GMI-W, asking that would be a tall order for AMD.

3rd time around, and possibly with CPU being more power efficient, what are the odds that AMD can manage to have the same boost clock for 9800x3d CPU as 9700x?

9700x already has much lower power consumption than 7700x and 7800 x3d. So, no clock regression would be a big win.

 

[SteinFG]

3rd time around, and possibly with CPU being more power efficient, what are the odds that AMD can manage to have the same boost clock for 9800x3d CPU as 9700 XT?

9700 XT already has much lower power consumption than 7700 XT and 7800 x3d. So, no clock regression would be a big win.

XT? there's no XT in Ryzen 9000 or 7000
I assume you mean X.
I think the 1t boost clock is not dependant on TDP figure, so i'm sceptical about that

 

[inf64]

All the tests were n-thread, no 1t tests.

That's very interesting and so different versus previous reveals of Zen. AMD always used 1T at fixed clock to showcase IPC changes in Zen reveals (prior to Zen 5).

Zen 4 had a 34% SMT uplift vs Zen2/3 which had ~25%



If Zen 5 has 25% SMT uplift then the ST IPC could end up being higher than what the slide shows.

 

[Joe NYC]

XT? there's no XT in Ryzen 9000 or 7000
I assume you mean X.
I think the 1t boost clock is not dependant on TDP figure, so i'm sceptical about that

Sorry, fixed, thanks.

 

[yuri69]

There are many questions floating in my head.

• completely new grounds-up design in development since 2018
• designer's dream
• magic frontend
• so much more resources, width, and depth
• finally a GLC level resources
• Zen 4 was anemic
• Zen 3 was a similar grounds-up design - but just reshuffling the components
• 100% op-sec - Osborning the entire lineup
• MLID got fake slides - disregard 10-15%
• 32-40% 1T

 

[coercitiv]

That's very interesting and so different versus previous reveals of Zen. AMD always used 1T at fixed clock to showcase IPC changes in Zen reveals (prior to Zen 5).

AMD IPC slide is a mess in terms of methodology or accuracy. They reference GNR-03, and here's what was posted already in the thread in terms of end notes:

Spoiler

They fixed the clocks to 4GHz, but were apparently comparing 16 vs 8 cores (9950X vs. 7700X). Obviously there's a mistake or omission somewhere, but if that is the case, what does one trust from this piece of information?

 

[igor_kavinski]

The Zen 5 vs. 4 IPC slide at 4 GHz isoclock (GNR-03) is using X670E chipset with DDR5-6000 for both CPUs but then AMD mentions this:



That leads me to believe that AMD is sandbagging Zen 5 max performance (both ST and MT).

Assuming X870E can work with DDR5-7200 EXPO kits, that could be a significant uplift in membw-hungry workloads.

So I'm gonna give AMD the benefit of the doubt until such time that some review site conclusively proves with a high end EXPO kit that there is no significant difference between Zen 5 scores at DDR5-6000 and whatever the higher speed EXPO kit runs at.

Sucks for existing X670 owners though if they are unable to use those premium EXPO kits with their chipset, due to lower quality traces on their mobos.

 

[inf64]

AMD IPC slide is a mess in terms of methodology or accuracy. They reference GNR-03, and here's what was posted already in the thread in terms of end notes:

Spoiler

View attachment 100319

They fixed the clocks to 4GHz, but were apparently comparing 16 vs 8 cores (9950X vs. 7700X). Obviously there's a mistake or omission somewhere, but if that is the case, what does one trust from this piece of information?

Thanks, the end notes are a mess indeed. If we assume there are no typos, why not test 8C Zen 5 vs 7700X? Weird choices of benchmarks where the are no 1T specific benchmarks as they did with Zen 2/ Zen 3/ Zen 4 reveals. Bizarre stuff.

 

[igor_kavinski]

"AMD Performance Labs" is such a joke. They have only succeeded in confusing us. I wonder if they came up with honest results and then marketing told them, no no. We want it like so and then they were forced to create the jumbled up mess that we got.

 

[Joe NYC]

There are many questions floating in my head.

• completely new grounds-up design in development since 2018
• designer's dream
• magic frontend
• so much more resources, width, and depth
• finally a GLC level resources
• Zen 4 was anemic
• Zen 3 was a similar grounds-up design - but just reshuffling the components
• 100% op-sec - Osborning the entire lineup
• MLID got fake slides - disregard 10-15%
• 32-40% 1T

Couple of things:

I have seen estimates of 74 and 78 mm2 die size, vs. ~70 mm2 for Zen 4. And that includes full AVX-512 for each of 8 cores. So, it seems like Zen 5 did not get all the resources, it is still very much on a diet.

Zen 4 was not anemic.

 

[igor_kavinski]

as they did with Zen 2/ Zen 3/ Zen 4 reveals. Bizzare stuff.

One would think they would create identical and consistent slides to previous launches so people can compare. Apparently that's too much to ask for...

 

[yuri69]

It's 3% less in IPC from Zen 3. I don't consider that a big miss personally, especially since IPC gets harder to extract.
But the actual problems are as follows:
1. Some people built a hype train, as usual
2. Clock rate didn't increase. Power TBD.
3. It wasn't a 16 month fast follow-up like Zen 3

Zen 5 was conveyed as a very deep Zen redesign. Zen 3 was not.
Clocks are problem since originally they probably targeted 3nm.
Zen 5 comes ~21months after the "COVID-delayed Zen 4".

The post mortem will be interesting, is the frontend not as bigly as we thought? PRFi or rob sizes smaller then expected? Not a large enough jump in prefetch / predict? If rob >512 and decode a complete rework then I will say zen5 is bulldozer tier execution, they just are in a much better place before hand and made far better architectural choices.

Intel's Lion Cove suddenly doesn't look like a disaster.

 

[inf64]

Zen 5 was conveyed as a very deep Zen redesign. Zen 3 was not.
Clocks are problem since originally they probably targeted 3nm.
Zen 5 comes ~21months after the "COVID-delayed Zen 4".


Intel's Lion Cove suddenly doesn't look like a disaster.

Actually Zen 3 was also a huge redesign, but they focused on shuffling and somewhat extending the existing stuff and making it way more efficient. Zen 3 was/is the best Zen "new" core after the original Zen. Zen 5 looks to be underwhelming (so far) when you count the changes they did and what it actually got to show for.

Edit:

From my guesswork estimate :

"Versus 7950X (vanilla):
29-30% higher ST performance
15-16% higher MT performance"

I pretty much nailed the average MT performance of 9950X, although we still have no idea at what effective clock speed it will run in MT workloads. I have failed miserably at ST IPC (overestimated) and missed the ST max clock (underestimated).

 

[PJVol]

I don't see the point in listing 1T workloads in an overall "geomean" IPC figure.

 

[tsamolotoff]

3rd time around, and possibly with CPU being more power efficient, what are the odds that AMD can manage to have the same boost clock for 9800x3d CPU as 9700x?

If the extra cache is again manufactured with dense process and glued the same way (looks like AMD decided to shave an extra 0.01c and just glue the structural silicon (tm) (C) on top of the cores ), highly unlikely in my opinion. Enterprise first, we peasants the last, duh.

 

[inf64]

I don't see the point in listing 1T workloads in an overall "geomean" IPC figure.

Well it makes sense to list them as it was the way they did it in the past. Zen 4 had a bigger SMT uplift (34% vs 25%) so it makes sense to list 1T and use same core count parts when doing the IPC comparison.

 

[leoneazzurro]

I don't see the point in listing 1T workloads in an overall "geomean" IPC figure.

It may be useful for separating the core potential from the thermal and power limitations.